參數(shù)資料
型號(hào): uPSD3412C-24U6T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和16Kbit SRAM的
文件頁數(shù): 110/152頁
文件大?。?/td> 796K
代理商: UPSD3412C-24U6T
UPSD3212C, UPSD3212CV
110/152
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 56):
I
MCU I/O Mode
I
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
I
CPLD Input – via the Input Macrocells (IMC)
I
In-System Programming (ISP) – JTAG pins
(TMS, TCK, TDI, TDO) are dedicated pins for
device programming. (See the section entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE,” page 118, for
more information on JTAG programming.)
I
Open Drain – Port C pins can be configured in
Open Drain Mode
I
Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
Standby (V
STBY
).
PC4 can be configured as a Battery-on Indicator
(V
BATON
), indicating when V
CC
is less than
V
BAT
.
Port C does not support Address Out Mode, and
therefore no Control Register is required.
Figure 56. Port C Structure
Note: 1. ISP or battery back-up
M
DATA OUT
REG.
D
Q
D
Q
WR
WR
MCELLBC[7:0]
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
INPUT
MACROCELL
ENABLE OUT
SPECIAL FUNCTION1
SPECIAL FUNCTION1
CONFIGURATION
BIT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT C PIN
DATA OUT
AI06618
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