參數(shù)資料
型號： UPSD3352DV-40U6T
廠商： 意法半導體
英文描述： Turbo Series Fast 8032 MCU with Programmable Logic
中文描述： Turbo系列8032微控制器的快速可編程邏輯
文件頁數(shù)： 62/231頁
文件大?。?/td> 3722K
代理商： UPSD3352DV-40U6T
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uPSD33xx
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MCU BUS INTERFACE
The MCU Module has a programmable bus inter-
face. It is based on a standard 8032 bus, with eight
data signals multiplexed with eight low-order ad-
dress signals (AD[7:0]). It also has eight high-or-
der non-multiplexed address signals (A[15:8]).
Time multiplexing is controlled by the address
latch signal, ALE.
This bus connects the MCU Module to the PSD
Module, and also connects to external pins only on
80-pin devices. See the AC specifications section
at the end of this document for external bus timing
on 80-pin devices.
Four types of data transfers are supported, each
transfer is to/from a memory location external to
the MCU Module:
–
Code Fetch cycle using the PSEN signal: fetch
a code byte for execution
–
Code Read cycle using PSEN: read a code
byte using the MOVC (Move Constant)
instruction
–
XDATA Read cycle using the RD signal: read
a data byte using the MOVX (Move eXternal)
instruction
–
XDATA Write cycle using the WR signal: write
a data byte using the MOVX instruction
The number of MCU_CLK periods for these trans-
fer types can be specified at runtime by firmware
writing to the SFR register named BUSCON (
Ta-
ble 35., page 63
). Here, the number of MCU_CLK
clock pulses per bus cycle are specified to maxi-
mize performance.
Important:
By default, the BUSCON Register is
loaded with long bus cycle times (6 MCU_CLK pe-
riods) after a reset condition. It is important that the
post-reset initialization firmware sets the bus cycle
times appropriately to get the most performance,
according to
Table 36., page 64
. Keep in mind that
the PSD Module has a faster Turbo Mode (default)
and a slower but less power consuming Non-Tur-
bo Mode. The bus cycle times must be pro-
grammed in BUSCON to optimize for each mode
as shown in
Table 36., page 64
. See
PLD Non-
Turbo Mode, page 192
for more details.
Bus Read Cycles (PSEN or RD)
When the PSEN signal is used to fetch a byte of
code, the byte is read from the PSD Module or ex-
ternal device and it enters the MCU Pre-Fetch
Queue (PFQ). When PSEN is used during a
MOVC instruction, or when the RD signal is used
to read a byte of data, the byte is routed directly to
the MCU, bypassing the PFQ.
Bits in the BUSCON Register determine the num-
ber of MCU_CLK periods per bus cycle for each of
these kinds of transfers to all address ranges.
It is not possible to specify in the BUSCON Regis-
ter a different number of MCU_CLK periods for
various address ranges. For example, the user
cannot specify 4 MCU_CLK periods for RD read
cycles to one address range on the PSD Module,
and 5 MCU_CLK periods for RD read cycles to a
different address range on an external device.
However, the user can specify one number of
clock periods for PSEN read cycles and a different
number of clock periods for RD read cycles.
Note 1:
A PSEN bus cycle in progress may be
aborted before completion if the PFQ and Branch
Cache (BC) determines the current code fetch cy-
cle is not needed.
Note 2:
Whenever the same number of MCU_CLK
periods is specified in BUSCON for both PSEN
and RD cycles, the bus cycle timing is typically
identical for each of these types of bus cycles. In
this case, the only time PSEN read cycles are
longer than RD read cycles is when the PFQ is-
sues a stall while reloading. PFQ stalls do not af-
fect RD read cycles. By comparison, in many
traditional 8051 architectures, RD bus cycles are
always longer than PSEN bus cycles.
Bus Write Cycles (WR)
When the WR signal is used, a byte of data is writ-
ten directly to the PSD Module or external device,
no PFQ or caching is involved. Bits in the BUS-
CON
Register
determine
MCU_CLK periods for bus write cycles to all ad-
dresses. It is not possible to specify in BUSCON a
different number of MCU_CLK periods for writes to
various address ranges.
Controlling the PFQ and BC
The BUSCON Register allows firmware to enable
and disable the PFQ and BC at run-time. Some-
times it may be desired to disable the PFQ and BC
to ensure deterministic execution. The dynamic
action of the PFQ and BC may cause varying pro-
gram execution times depending on the events
that happen prior to a particular section of code of
interest. For this reason, it is not recommended to
implement timing loops in firmware, but instead
use one of the many hardware timers in the
uPSD33xx.
By default, the PFQ and BC are enabled after a re-
set condition.
Important:
Disabling the PFQ or BC will seriously
reduce MCU performance.
the
number
of
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UPSD3354D-40T6 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
UPSD3354D-40U6 功能描述:8位微控制器 -MCU 8BIT Fast 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
UPSD3354DV-40T6 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
UPSD3354DV-40U6 功能描述:8位微控制器 -MCU FAST 8032 8BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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