- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361594 > UPSD3352DV-40U6T (意法半導(dǎo)體) Turbo Series Fast 8032 MCU with Programmable Logic PDF資料下載
參數(shù)資料
| 型號(hào)： | UPSD3352DV-40U6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Turbo Series Fast 8032 MCU with Programmable Logic |
| 中文描述： | Turbo系列8032微控制器的快速可編程邏輯 |
| 文件頁(yè)數(shù)： | 156/231頁(yè) |
| 文件大?。?/td> | 3722K |
| 代理商： | UPSD3352DV-40U6T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)當(dāng)前第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)
uPSD33xx
156/231
PLDs.
The PSD Module contains two PLDs: the
Decode PLD (DPLD), and the General PLD
(GPLD), as shown in
Figure 63., page 157
. Both
PLDs are fed by a common PLD input signal bus,
and additionally, the GPLD is connected to the
8032 data bus.
PLD logic is specified using PSDsoft Express and
programmed into the PSD Module using the JTAG
ISP channel. PLD logic is non-volatile and avail-
able at power-up. PLDs may not be programmed
by the 8032. The PLDs have selectable levels of
performance and power consumption.
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generate External Chip-Select
(ECS1-ECS2) signals on Port D.
The GPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, encoding and decoding logic. These logic
functions can be constructed from a combination
of 16 Output Macrocells (OMC), 20 Input Macro-
cells (IMC), and the AND-OR Array.
Routing of the 16 OMCs outputs can be divided
between pins on three Ports A, B, or C by the OMC
Allocator as shown in
Figure 67., page 163
. Eight
of the 16 OMCs that can be routed to pins on Port
A or Port B and are named MCELLAB0-
MCELLAB7. The other eight OMCs to be routed to
pins on Port B or Port C and are named
MCELLBC0-MCELLBC7. This routing depends on
the pin number assignments that are specified in
PSDsoft Express for “PLD Outputs” in the Pin Def-
inition section. OMC outputs can also be routed in-
ternally (not to pins) used as buried nodes to
create shifters, counters, etc.
The AND-OR Array is used to form product terms.
These product terms are configured from the logic
definitions entered in PSDsoft Express. A PLD In-
put Bus consisting of 69 signals is connected to
both PLDs. Input signals are shown in Table
84
,
both the true and compliment versions of each of
these signals are available at inputs to each PLD.
Note:
The 8032 data bus, D0 - D7, does not route
directly to PLD inputs. Instead, the 8032 data bus
has indirect access to the GPLD (not the DPLD)
when the 8032 reads and writes the OMC and IMC
registers within csiop address space.
Turbo Bit and PLDs.
The PLDs can minimize
power consumption by going to standby after ALL
the PLD inputs remain unchanged for an extended
time (about 70ns). When the Turbo Bit is set to log-
ic one (Bit 3 of the csiop PMMR0 Register), Turbo
mode is turned off and then this automatic standby
mode is achieved. Turning off Turbo mode in-
creases propagation delays while reducing power
consumption. The default state of the Turbo Bit is
logic zero, meaning Turbo mode is on. Additional-
ly, four bits are available in the csiop PMMR0 and
PMMR2 Registers to block the 8032 bus control
signals (RD, WR, PSEN, ALE) from entering the
PLDs. This reduces power consumption and can
be used only when these 8032 control signals are
not used in PLD logic equations. See
Power
Management, page 187
.
Table 84. DPLD and GPLD Inputs
Input Source
Input Name
Number
of
Signals
8032 Address Bus
A0-A15
16
8032 Bus Control Signals
PSEN, RD, WR,
ALE
4
Reset from MCU Module
RESET
1
Power-Down from Auto-
Power Down Counter
PDN
1
PortA Input Macrocells
(80-pin devices only)
PA0-PA7
8
PortB Input Macrocells
PB0-PB7
8
PortC Input Macrocells
PC2, PC3, PC4,
PC7
4
Port D Inputs
(52-pin devices have only
PD1)
PD1, PD2
2
Page Register
PGR0-PGR7
8
Macrocell OMC bank AB
Feedback
MCELLAB
FB0-7
8
Macrocell OMC bank BC
Feedback
MCELLBC
FB0-7
8
Flash memory Status Bit
Ready/Busy
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPSD3353DV-40T6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3353DV-40U6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD3354DV-40T6T | Turbo Series Fast 8032 MCU with Programmable Logic |
| UPSD33XX | Fast 8032 MCU with Programmable Logic |
| uPSD3412C-24U6T | Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3354D-40T6 | 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354D-40U6 | 功能描述:8位微控制器 -MCU 8BIT Fast 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354DV-40T6 | 功能描述:8位微控制器 -MCU 8032 MCU USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3354DV-40U6 | 功能描述:8位微控制器 -MCU FAST 8032 8BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3422E-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。