參數(shù)資料
型號(hào)： UPD98404GJ-KEU
廠商： NEC Corp.
英文描述： E Core
中文描述： 高級(jí)自動(dòng)柜員機(jī)的SONET成幀器
文件頁數(shù)： 19/36頁
文件大?。?/td> 201K
代理商： UPD98404GJ-KEU
Data Sheet S11822EJ4V0DS00
19
μ
PD98404
Management Interface
a) Internal register read
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Address setup time (to DS_B
↓
[RD_B
↓
])
t
SADDS
10
ns
CS_B setup time (to DS_B
↓
[RD_B
↓
])
t
SCSDS
5
9
×
t
CYTK
ns
R/W_B[WR_B] setup time
(to DS_B
↓
[RD_B
↓
])
t
SRWDS
5
ns
Address hold time (to DS_B
↑
[RD_B
↑
])
t
HADDS
4
ns
CS_B hold time (to DS_B
↑
[RD_B
↑
])
t
HCSDS
0
ns
R/W_B [WR_B] hold time
(to DS_B
↑
[RD_B
↑
])
t
HRWDS
4
ns
DS_B
↓
[RD_B
↓
]
→
ACK_B [RDY_B]
output delay time
t
VAKDS
Load capacity = 50 pF
15
ns
DS_B
↓
[RD_B
↓
]
→
data output delay
time
t
VDADS
Load capacity = 50 pF
20
ns
DS_B
↑
[RD_B
↑
]
→
ACK_B [RDY_B] float
delay time
t
IAKDSR
Load capacity = 50 pF
5
30
ns
DS_B
↑
[RD_B
↑
]
→
data float delay time
t
IDADS
Load capacity = 50 pF
15
45
ns
ACK
↓
→
data output delay time
t
DDAAK
Load capacity = 50 pF
10
ns
DS_B[RD_B] pulse width
Note
t
WDS
50
ns
DS_B
↑
[RD_B
↑
]
→
DS_B
↓
[RD_B
↓
]
↓
recovery time
t
DSINT
4
×
t
CYTK
ns
Note
t
WDS
defines the time during which the
μ
PD98404 can recognize DS_B [RD_B] as a low level, and does not
define the pulse width of DS_B [RD_B] with which data can be accurately read.
The time required for the
μ
PD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low differs
depending on the register to be accessed. Make DS_B [RD_B] high after confirming that ACK_B [RDY_B].
The time required for the
μ
PD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low is “4 x
TCLK clock cycle (t
CYTK
)” at best. So that any register can be read without using ACK_B [RDY_B], widen
the pulse width of DS_B [RD_B] to at least to “4 x TCLK clock cycle”.
Remark
t
CYTK
is the cycle of the TCLK clock.
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