參數(shù)資料
型號(hào)： UPD98404GJ-KEU
廠商： NEC Corp.
英文描述： E Core
中文描述： 高級(jí)自動(dòng)柜員機(jī)的SONET成幀器
文件頁(yè)數(shù)： 1/36頁(yè)
文件大?。?/td> 201K
代理商： UPD98404GJ-KEU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD98404
ADVANCED ATM SONET FRAMER
Document No. S11822EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
1997, 1999
DESCRIPTION
The
μ
PD98404 NEASCOT-P30
connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI
provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the
ATM Forum’s UNI3.1 recommendations.
This product’s main functions include transmission functions such as mapping of ATM cells sent from the ATM
layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media
Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM
cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition,
this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and
a clock synthesis function that generates a clock for transmissions.
TM
is an LSI for ATM applications, which can be used in ATM adapter boards for
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
μ
PD98404 User’s Manual: S11821E
FEATURES
On-chip clock recovery/clock synthesis functions
Provides TC sub-layer function for the ATM protocol’s physical layer
Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1
Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)
Supports three UTOPIA interfaces:
Single PHY octet-level handshaking
Single PHY cell-level handshaking
Multi PHY mode
Selectable to drop/bypass unassigned cells
On-chip internal loopback functions for PMD layer loopback and ATM layer loopback
Supports two PMD interfaces: serial and parallel
155.52 Mbps serial interface
19.44 MHz parallel interface
Provides registers for writing/reading overhead information
SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte
LOH (line overhead)
:K1 byte, K2 byte
POH (path overhead)
:F2 byte, C2 byte, H4 byte
Provides pseudo error frame transmit function for various errors
Supports JTAG boundary scan test function (IEEE 1149.1)
CMOS technology
+3.3 V single power supply
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