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參數資料
| 型號： | UPF01002 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 1/2頁 |
| 文件大?。?/td> | 165K |
| 代理商： | UPF01002 |
N e v e r s t o p t h i n k i n g .
UPF 01002
CORE and ITU-T G.825
■
Supports various clocking
modes based on external refer-
ence clocks, loop- and external
timing
■
Integrated bit error rate tester
(BERT) usable for multiple at-
speed diagnostic scenarios
■
Includes the XGXS, PCS, WIS,
and PMA sublayers of the OSI
protocol stack
■
Synchronization and de-skewing
of XAUI lanes
■
Integrated standard STS-192/
STM-64 SONET/SDH framer
according to GR-253-CORE,
ANSI T1. 105/416, ITU-T G.707.
■
Optionally maps/extracts
10 Gbit/s Ethernet packets into/
from the STS-192c/VC4-64c
payload or conveys them to the
serial interface directly
■
P
R O D U C T
B
R I E F
U P F 0 1 0 0 2
TenGiPHY
-W
Applications
■
Fiber optic modules according to
the XENPAK multi-source
agreement
■
10 Gbit/s Ethernet and Fibre
Channel line cards
■
Ethernet backbones in Metro
Area Networks
■
Terabit Routers
Features
■
Complete 10 Gbit/s Ethernet and
Fibre Channel PHY supporting
WAN and LAN applications
■
Complies with IEEE 802.3ae
■
Compliant to XENPAK multi-
source agreement
■
Complies with ANSI 1413-D
■
Embedded μController allows for
control and tuning of the PMDs
via analog interfaces
■
Clock & data recovery and clock
multiplying unit without external
loop filter components
■
Complies with jitter tolerance
and jitter transmit requirements
according to Telcordia GR-1244-
■
Performance monitoring accord-
ing to ANSI T1. 231
■
Various loop back modes for
system debugging
■
Provides access to E2PROM via
I2C interface according to XEN-
PAK requirements; automatic
E2PROM download on power-up
■
Power-efficient design:
<1.3W @ 1.3V
Interfaces
■
Full duplex, XFI compliant serial
CML line interface for data rates
between 9.95 and 10.5 Gbit/s
■
Quad serial Gbit/s XAUI interface
with data rates between 3.1 and
3.2 Gbit/s
MDIO interface
I2C bus interface
XENPAK diagnostic interface
providing eight 12-bit ADCs and
four 10-bit DACs
IEEE 1149.1 JTAG boundary
scan interface
■
■
■
10 Gigabit/s Ethernet Trans-
ceiver with OC-192c Framer
and XAUI Interface
The TenGiPHY
-W is a single chip transceiver IC
for 10 Gbit/s Ethernet and Fibre Channel connec-
tivity. It offers a serial, full duplex 10 Gbit/s inter-
face to an optical sub-module. The integrated
CDR and CMU operate at data rates between
9.95328 and 10.51875Gbit/s. The TenGiPHY-W pro-
vides the XGXS, PCS and PMA sublayers of the
10G Ethernet and Fibre Channel standards. For
WAN applications a standard OC-192/STM-64
SONET/SDH framer together with flexible clocking
modes enables a direct connection to the public
network without additional components.
The networking system can control the chip via a
narrow-width MDIO interface by writing and read-
ing its control and status registers.
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