參數(shù)資料
型號: UPD98404
廠商: NEC Corp.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 24/36頁
文件大?。?/td> 201K
代理商: UPD98404
Data Sheet S11822EJ4V0DS00
24
μ
PD98404
(ii) Write timing
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Address setup time (to CS_B
)
t
SADCS
10
ns
R/W_B setup time (to CS_B
)
t
SRWCS
10
ns
Data setup time (to CS_B
)
t
SDACS
10
ns
Address hold time (to CS_B
)
t
HADCSW
10
ns
R/W_B hold time (to CS_B
)
t
HRWCSW
10
ns
Data hold time (to CS_B
)
t
HDACS
10
ns
CS_B pulse width
t
WCS
4
×
t
CYTK
ns
Remark
t
CYTK
is the cycle of the TCLK clock.
MADD0-MADD6
CS_B
MD0-MD7
DS_B
R/W_B
t
SADDS
t
HRWCSW
t
HADCSW
t
WCS
t
SDACS
t
HDACS
t
SRWCS
Data
Caution
If the device is reset via software by setting the CMR2 register, do not read or write all the registers
for the duration of at least “20 x TCLK clock cycle (t
CYTK
)” from that write cycle. Otherwise, the
registers may not be read or written correctly.
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