μPD78F920x ONLY) User’s Manual U18172EJ3V0UD 103 Figure 6-13." />
參數(shù)資料
型號: UPD78F9201MA-CAC-A
廠商: Renesas Electronics America
文件頁數(shù): 8/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 2KB FLASH 128B RAM
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 7
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LSSOP(0.225",5.72mm 寬)
包裝: 托盤
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (
μPD78F920x ONLY)
User’s Manual U18172EJ3V0UD
103
Figure 6-13. Timing of Interval Timer Operation
Count clock
t
TM00 count value
CR000
INTTM000
0000H
0001H
N
0000H 0001H
N
0000H 0001H
N
Timer operation enabled
Clear
Interrupt request generated
Remark
Interval time = (N + 1)
× t
N = 0001H to FFFFH (settable range)
When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare
register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,
overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)
before the change, it is necessary to restart the timer after changing CR000.
Figure 6-14. Timing After Change of Compare Register During Timer Count Operation (N
→ M: N > M )
CR000
NM
Count clock
TM00 count value
X – 1
X
FFFFH
0000H
0001H
0002H
Remark
N > X > M
6.4.2
External event counter operation
Setting
The basic operation setting procedure is as follows.
<1>
Set the CRC00 register (see Figure 6-15 for the set value).
<2>
Set the count clock by using the PRM00 register.
<3>
Set any value to the CR000 register (0000H cannot be set).
<4>
Set the TMC00 register to start the operation (see Figure 6-15 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
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