參數(shù)資料
型號： UPD78F9201MA-CAC-A
廠商： Renesas Electronics America
文件頁數(shù)： 130/158頁
文件大?。?/td> 0K
描述： MCU 8BIT 2KB FLASH 128B RAM
標準包裝： 400
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 7
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 4x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 10-LSSOP（0.225"，5.72mm 寬）
包裝： 托盤
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18172EJ3V0UD
71
4.4
Operation of Port Function
The operation of a port differs, as follows, depending on the setting of the I/O mode.
Caution
Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit
units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not
subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and
outputs.
4.4.1
Writing to I/O port
(1) In output mode
A value can be written to the output latch by a transfer instruction. In addition, the contents of the output latch are
output from the pin. Once data is written to the output latch, it is retained until new data is written to the output
latch.
When a reset signal is generated, cleans the data in the output latch.
(2) In input mode
A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the
pin status remains unchanged.
Once data is written to the output latch, it is retained until new data is written to the output latch.
When a reset signal is generated, cleans the data in the output latch.
4.4.2
Reading from I/O port
(1) In output mode
The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain
unchanged.
(2) In input mode
The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged.
4.4.3
Operations on I/O port
(1) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch. The
contents of the output latch are output from the pin.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Reset signal generation clears the data in the output latch.
(2) In input mode
The pin level is read and an operation is performed on its contents. The operation result is written to the output
latch. However, the pin status remains unchanged because the output buffer is off.
When a reset signal is generated, cleans the data in the output latch.
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