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參數(shù)資料
| 型號(hào)： | UPD78C12AGQ |
| 廠商： | NEC Corp. |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER WITH A/D CONVERTER |
| 中文描述： | 8位單片機(jī)與A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 39/66頁 |
| 文件大?。?/td> | 3252K |
| 代理商： | UPD78C12AGQ |
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39
μ
PD78C10A,78C11A,78C12A
AC CHARACTERISTICS
(T
A
= –40 to +85
°
C, V
DD
= AV
DD
= +5.0 V
±
10 %, V
SS
= AV
SS
= 0 V)
Read/write Operation:
f
XX
= 15 MHz, C
L
= 100 pF
RD low level width
t
RR
f
XX
= 15 MHz
f
XX
= 15 MHz, C
L
= 100 pF
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
X1 input cycle time
t
CYC
66
250
ns
Address setup time (to ALE
↓
)
t
AL
30
ns
Address hold time (from ALE
↓
)
t
LA
f
XX
= 15 MHz, CL = 100 pF
35
ns
RD
↓
delay time from address
t
AR
100
ns
Address float time from RD
↓
t
AFR
C
L
= 100 pF
20
ns
Data input time from address
t
AD
250
ns
Data input time from ALE
↓
t
LDR
135
ns
Data input time from RD
↓
t
RD
120
ns
RD
↓
delay time from ALE
↓
t
LR
15
ns
Data hold time (from RD
↑
)
t
RDH
C
L
= 100 pF
0
ns
ALE
↑
delay time from RD
↑
t
RL
f
XX
= 15 MHz, C
L
= 100 pF
80
ns
In Data Read
f
XX
= 15 MHz, C
L
= 100 pF
215
ns
In OP Code Fetch
f
XX
= 15 MHz, C
L
= 100 pF
415
ns
ALE high level width
t
LL
f
XX
= 15 MHz, C
L
= 100 pF
90
ns
M1 setup time (to ALE
↓
)
t
ML
30
ns
M1 hold time (from ALE
↓
)
t
LM
35
ns
IO/M setup time (to ALE
↓
)
t
IL
30
ns
IO/M hold time (from ALE
↓
)
t
LI
35
ns
t
AW
100
ns
Data output time from ALE
↓
t
LDW
180
ns
Data output time from WR
↓
t
WD
C
L
= 100 pF
100
ns
WR
↓
delay time from ALE
↓
t
LW
15
ns
Data setup time (to WR
↑
)
t
DW
165
ns
Data hold time (from WR
↑
)
t
WDH
f
XX
= 15 MHz, C
L
= 100 pF
60
ns
ALE
↑
delay time from WR
↑
t
WL
80
ns
WR low level width
t
WW
215
ns
WR
↓
delay time from address
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