參數(shù)資料
型號(hào)： UPD784224Y
廠商： NEC Corp.
英文描述： 16/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16/8-BIT單晶片微控制器
文件頁(yè)數(shù)： 73/92頁(yè)
文件大?。?/td> 687K
代理商： UPD784224Y
73
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
(d) I
2
C bus mode (
μ
PD784225Y only)
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
f
CLK
0
100
0
400
kHz
Bus free time (between stop
and start conditions)
t
BUF
4.7
1.3
μ
s
Hold time
Note1
t
HD : STA
4.0
0.6
μ
s
Low-level width of SCL0
clock
t
LOW
4.7
1.3
μ
s
High-level width of SCL0
clock
t
HIGH
4.0
0.6
μ
s
Setup time of start/restart
conditions
t
SU : STA
4.7
0.6
μ
s
Data hold When using
time
CBUS-compatible
master
t
HD : DAT
5.0
μ
s
When using I
2
C
bus
0
Note 2
0
Note 2
0.9
Note 3
μ
s
Data setup time
t
SU : DAT
250
100
Note 4
ns
Rising time of SDA0 and
SCL0 signals
t
R
1,000
20 + 0.1Cb
Note 5
300
ns
Falling time of SDA0 and
SCL0 signals
t
F
300
20 + 0.1Cb
Note 5
300
ns
Setup time of stop condition
t
SU : STO
4.0
0.6
μ
s
Pulse width of spike
restricted by input filter
t
SP
0
50
ns
Load capacitance of each
bus line
Cb
400
400
pF
Notes 1.
For the start condition, the first clock pulse is generated after the hold time.
2.
To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on V
IHmin.
) with at least 300 ns of hold time.
3.
If the device does not extend the SCL0 signal low-level hold time (t
LOW
), only the maximum data hold
time t
HD : DAT
needs to be satisfied.
4.
The high-speed mode I
2
C bus can be used in a standard mode I
2
C bus system. In this case, the
conditions described below must be satisfied.
If the device does not extend the SCL0 signal low-level hold time
t
SU : DAT
≥
250 ns
If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t
Rmax.
+ t
SU : DAT
=
1,000 + 250 = 1,250 ns by standard mode I
2
C bus specification)
5.
Cb: Total capacitance per bus line (unit: pF)
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