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68
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
AC Characteristics
(T
A
=
40
°
C to +85
°
C, V
DD
= V
DD0
= V
DD1
= AV
DD
= 1.8 to 5.5 V, V
SS
= V
SS0
= V
SS1
= AV
SS
= 0 V)
(1) Read/write operation (2/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Delay time from ASTB
↓
to RD
↓
t
DSTR
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
V
DD
= 2.0 V
±
10%
0.5T
20
ns
Data hold time (from RD
↑
)
t
HRID
V
DD
= 5.0 V
±
10%
0
ns
V
DD
= 3.0 V
±
10%
0
ns
V
DD
= 2.0 V
±
10%
0
ns
Address active time from
RD
↑
t
DRA
V
DD
= 5.0 V
±
10%
0.5T
2
ns
V
DD
= 3.0 V
±
10%
0.5T
12
ns
V
DD
= 2.0 V
±
10%
0.5T
35
ns
Delay time from RD
↑
to
ASTB
↑
t
DRST
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
V
DD
= 2.0 V
±
10%
0.5T
40
ns
RD low-level width
t
WRL
V
DD
= 5.0 V
±
10%
(1.5 + n) T
25
ns
V
DD
= 3.0 V
±
10%
(1.5 + n) T
30
ns
V
DD
= 2.0 V
±
10%
(1.5 + n) T
25
ns
Delay time from address to
WR
↓
t
DAW
V
DD
= 5.0 V
±
10%
(1 + a) T
24
ns
V
DD
= 3.0 V
±
10%
(1 + a) T
34
ns
V
DD
= 2.0 V
±
10%
(1 + a) T
70
ns
Address hold time
(from WR
↑
)
t
HRD
V
DD
= 5.0 V
±
10%
0.5T
14
ns
V
DD
= 3.0 V
±
10%
0.5T
14
ns
V
DD
= 2.0 V
±
10%
0.5T
14
ns
Delay time from ASTB
↓
to
data output
t
DSTOD
V
DD
= 5.0 V
±
10%
0.5T + 15
ns
V
DD
= 3.0 V
±
10%
0.5T + 30
ns
V
DD
= 2.0 V
±
10%
0.5T + 240
ns
Delay time from WR
↓
to
data output
t
DWOD
V
DD
= 5.0 V
±
10%
0.5T
30
ns
V
DD
= 3.0 V
±
10%
0.5T
30
ns
V
DD
= 2.0 V
±
10%
0.5T
30
ns
Delay time from ASTB
↓
to
t
DSTW
V
DD
= 5.0 V
±
10%
0.5T
9
ns
WR
↓
V
DD
= 3.0 V
±
10%
0.5T
9
ns
V
DD
= 2.0 V
±
10%
0.5T
20
ns
Data setup time (to WR
↑
)
t
SODWR
V
DD
= 5.0 V
±
10%
(1.5 + n) T
20
ns
V
DD
= 3.0 V
±
10%
(1.5 + n) T
25
ns
V
DD
= 2.0 V
±
10%
(1.5 + n) T
70
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: Main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)