參數(shù)資料
型號： UPD784224Y
廠商： NEC Corp.
英文描述： 16/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16/8-BIT單晶片微控制器
文件頁數(shù)： 67/92頁
文件大?。?/td> 687K
代理商： UPD784224Y
67
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
AC Characteristics
(T
A
=
40
°
C to +85
°
C, V
DD
= V
DD0
= V
DD1
= AV
DD
= 1.8 to 5.5 V, V
SS
= V
SS0
= V
SS1
= AV
SS
= 0 V)
(1) Read/write operation (1/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Cycle time
t
CYK
4.5 V
≤
V
DD
≤
5.5 V
80
ns
2.7 V
≤
V
DD
< 4.5 V
160
ns
2.0 V
≤
V
DD
< 2.7 V
320
ns
1.8 V
≤
V
DD
< 2.0 V
500
ns
Address setup time
(to ASTB
↓
)
t
SAST
V
DD
= 5.0 V
±
10%
(0.5 + a) T
20
ns
V
DD
= 3.0 V
±
10%
(0.5 + a) T
40
ns
V
DD
= 2.0 V
±
10%
(0.5 + a) T
80
ns
Address hold time
(from ASTB
↓
)
t
HSTLA
V
DD
= 5.0 V
±
10%
0.5T
19
ns
V
DD
= 3.0 V
±
10%
0.5T
24
ns
V
DD
= 2.0 V
±
10%
0.5T
34
ns
ASTB high-level width
t
WSTH
V
DD
= 5.0 V
±
10%
(0.5 + a) T
17
ns
V
DD
= 3.0 V
±
10%
(0.5 + a) T
40
ns
V
DD
= 2.0 V
±
10%
(0.5 + a) T
110
ns
Address hold time
(from RD
↑
)
t
HRA
V
DD
= 5.0 V
±
10%
0.5T
14
ns
V
DD
= 3.0 V
±
10%
0.5T
14
ns
V
DD
= 2.0 V
±
10%
0.5T
14
ns
Delay time from address to
RD
↓
t
DAR
V
DD
= 5.0 V
±
10%
(1 + a) T
24
ns
V
DD
= 3.0 V
±
10%
(1 + a) T
35
ns
V
DD
= 2.0 V
±
10%
(1 + a) T
80
ns
Address float time
(from RD
↓
)
t
FAR
V
DD
= 5.0 V
±
10%
0
ns
V
DD
= 3.0 V
±
10%
0
ns
V
DD
= 2.0 V
±
10%
0
ns
Data input time from
address
t
DAID
V
DD
= 5.0 V
±
10%
(2.5 + a + n) T
37
ns
V
DD
= 3.0 V
±
10%
(2.5 + a + n) T
52
ns
V
DD
= 2.0 V
±
10%
(2.5 + a + n) T
120
ns
Data input time from ASTB
↓
t
DSTID
V
DD
= 5.0 V
±
10%
(2 + n) T
35
ns
V
DD
= 3.0 V
±
10%
(2 + n) T
50
ns
V
DD
= 2.0 V
±
10%
(2 + n) T
80
ns
Data input time from RD
↓
t
DRID
V
DD
= 5.0 V
±
10%
(1.5 + n) T
40
ns
V
DD
= 3.0 V
±
10%
(1.5 + n) T
50
ns
V
DD
= 2.0 V
±
10%
(1.5 + n) T
90
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: Main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
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