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31
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
Table 7-1. Port Functions
Port Name
Pin Name
Function
Specification of Pull-up Resistor
Connection by Software
Port 0
P00 to P05
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 1
P10 to P17
Input port
—
Port 2
P20 to P27
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 3
P30 to P37
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 4
P40 to P47
Can be set in input or output mode bit-wise
Can directly drive LEDs
Can be specified in 1-port units
Port 5
P50 to P57
Can be set in input or output mode bit-wise
Can directly drive LEDs
Can be specified in 1-port units
Port 6
P60 to P67
Can be set in input or output mode bit-wise
Can be specified in 1-port units
Port 7
P70 to P72
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 12
P120 to P127
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 13
P130, P131
Can be set in input or output mode bit-wise
—
7.2 Clock Generator
An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider.
If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider
to reduce the current consumption.
Figure 7-2. Block Diagram of Clock Generator
XT2
XT1
X1
X2
STOP and bit 2 (MCK) of the
standby control register (STBC)
= 1 when the subsystem clock
is selected as CPU clock
Main system
clock
oscillator
Subsystem
clock
oscillator
f
XT
Watch timer,
clock output
function
Clock to
peripheral
hardware
CPU
clock
(f
CPU
)
Frequency
divider
Prescaler
Prescaler
STOP,
IDLE
controller
HALT
controller
f
X
f
X
2
f
XX
2
f
XX
2
2
f
XX
2
3
f
XX
S
S
IDLE
controller
Internal
system
clock
(f
CLK
)