參數(shù)資料
型號: UPD784037Y
廠商: NEC Corp.
英文描述: 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 16-/8-bit的單晶片微控制器
文件頁數(shù): 72/94頁
文件大?。?/td> 503K
代理商: UPD784037Y
μ
PD784035Y, 784036Y, 784037Y, 784038Y
72
(3) IOE1, IOE2
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
(SCK1, SCK2)
t
CYSK1
Input
V
DD
= +5.0 V
±
10%
250
500
ns
ns
Output
Internal clock divided by 16
T
ns
Serial clock low-level
width (SCK1, SCK2)
t
WSKL1
Input
V
DD
= +5.0 V
±
10%
85
210
ns
ns
Output
Internal clock divided by 16
0.5T–40
ns
Serial clock high-level
width (SCK1, SCK2)
t
WSKH1
Input
V
DD
= +5.0 V
±
10%
85
210
ns
ns
Output
Internal clock divided by 16
0.5T–40
ns
SI1, SI2 setup time
(to SCK1, SCK2
)
t
SSSK1
40
ns
SI1, SI2 hold time
(from SCK1, SCK2
)
t
HSSK1
40
ns
SO1, SO2 output delay time
(from SCK1, SCK2
)
t
DSOSK
0
50
ns
SO1, SO2 output hold time
(from SCK1, SCK2
)
t
HSOSK
During data transfer
0.5t
CYSK1
–40
ns
Remarks 1.
The values in this table are those when C
L
is 100 pF.
2.
T: Serial clock cycle set by software. The minimum value is 16/f
XX
.
(4) UART, UART2
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASCK clock input cycle
time
t
CYASK
V
DD
= +5.0 V
±
10%
125
ns
250
ns
ASCK clock low-level
width
t
WASKL
V
DD
= +5.0 V
±
10%
52.5
ns
85
ns
ASCK clock high-level
width
t
WASKH
V
DD
= +5.0 V
±
10%
52.5
ns
85
ns
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