參數(shù)資料
型號(hào)： UPD784037Y
廠商： NEC Corp.
英文描述： 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16-/8-bit的單晶片微控制器
文件頁(yè)數(shù)： 70/94頁(yè)
文件大小： 503K
代理商： UPD784037Y
μ
PD784035Y, 784036Y, 784037Y, 784038Y
70
(3) External wait timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT
↓
input time from
address
t
DAWT
V
DD
= +5.0 V
±
10%
(2+a)T–40
(2+a)T–60
1.5T–40
1.5T–60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT
↓
input time from
ASTB
↓
t
DSTWT
V
DD
= +5.0 V
±
10%
WAIT hold time from
ASTB
↓
t
HSTWTH
V
DD
= +5.0 V
±
10%
(0.5+n)T+5
(0.5+n)T+10
WAIT
↑
delay time from
ASTB
↓
t
DSTWTH
V
DD
= +5.0 V
±
10%
(1.5+n)T–40
(1.5+n)T–60
T–50
T–70
WAIT
↓
input time from
RD
↓
t
DRWTL
V
DD
= +5.0 V
±
10%
WAIT
↓
hold time from
RD
↓
t
HRWT
V
DD
= +5.0 V
±
10%
nT+5
nT+10
WAIT
↑
delay time from
RD
↓
t
DRWTH
V
DD
= +5.0 V
±
10%
(1+n)T–40
(1+n)T–60
0.5T–5
0.5T–10
Data input time from
WAIT
↑
t
DWTID
V
DD
= +5.0 V
±
10%
WR
↑
delay time from
WAIT
↑
RD
↑
delay time from
WAIT
↑
WAIT
↓
input time from
WR
↓
t
DWTW
0.5T
t
DWTR
0.5T
ns
t
DWWTL
V
DD
= +5.0 V
±
10%
T–5
T–75
ns
ns
ns
ns
ns
ns
WAIT hold time from
WR
↓
t
HWWT
V
DD
= +5.0 V
±
10%
nT+5
nT+10
WAIT
↑
delay time from
WR
↓
t
DWWTH
V
DD
= +5.0 V
±
10%
(1+n)T–40
(1+n)T–70
Remark
T: T
CYK
(system clock cycle time)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
(4) Refresh timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Random read/write cycle
time
REFRQ low-level pulse
width
t
RC
3T
ns
t
WRFQL
V
DD
= +5.0 V
±
10%
1.5T–25
1.5T–30
0.5T–9
ns
ns
ns
REFRQ delay time from
ASTB
↓
REFRQ delay time from
RD
↑
REFRQ delay time from
WR
↑
ASTB delay time from
REFRQ
↑
REFRQ high-level pulse
width
t
DSTRFQ
t
DRRFQ
1.5T–9
ns
t
DWRFQ
1.5T–9
ns
t
DRFQST
0.5T–15
ns
t
WRFQH
V
DD
= +5.0 V
±
10%
1.5T–25
1.5T–30
ns
ns
Remark
T: T
CYK
(system clock cycle time)
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