參數(shù)資料
型號(hào): UPD784031YGC-3B9
廠商: NEC Corp.
英文描述: 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 16-/8-bit的單晶片微控制器
文件頁(yè)數(shù): 66/88頁(yè)
文件大小: 464K
代理商: UPD784031YGC-3B9
66
μ
PD784031Y
Serial Operation (T
A
= –40 to +85
°
C, V
DD
= +2.7 to 5.5 V, AV
SS
= V
SS
= 0 V)
(1) CSI
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Serial clock cycle time (SCK0)
t
CYSK0
Input
External clock
when SCK0, SO0 are CMOS
input/output
10/f
XX
+ 380
ns
Output
T
μ
s
Serial clock low-level width
(SCK0)
t
WSKL0
Input
External clock
when SCK0, SO0 are CMOS
input/output
5/f
XX
+ 150
ns
Output
0.5T – 40
μ
s
Serial clock high-level width
(SCK0)
t
WSKH0
Input
External clock
when SCK0, SO0 are CMOS
input/output
5/f
XX
+ 150
ns
Output
0.5T – 40
μ
s
SI0 setup time (to SCK0
)
t
SSSK0
40
ns
SI0 hold time (from SCK0
)
t
HSSK0
5/f
XX
+ 40
ns
SO0 output delay time
(from SCK0
)
t
DSBSK1
CMOS push-pull output
(3-wire serial I/O mode)
0
5/f
XX
+ 150
ns
t
DSBSK2
Open drain output
(2-wire serial I/O mode), R
L
= 1 k
0
5/f
XX
+ 400
ns
Remarks 1.
The values shown in the table above are those in the condition of C
L
= 100 pF.
2.
T : serial clock cycle set by the software. The minimum value is 16/f
XX
.
3.
f
XX
: oscillation frequency
(2) I
2
C
Parameter
Symbol
Standard Mode I
2
C Bus
f
XX
= 4 to 32 MHz
High-speed Mode I
2
C Bus
f
XX
= 8 to 32 MHz
Unit
MIN.
MAX.
MIN.
MAX.
SCL clock frequency
f
SCL
0
100
0
400
kHz
Low status hold time of SCL
clock
t
LOW
4.7
1.3
μ
s
High status hold time of SCL
clock
t
HIGH
4.0
0.6
μ
s
Data hold time
t
HD
; DAT
300
300
900
ns
Data setup time
t
SU
; DAT
250
100
ns
SDA, SCL signal rise time
t
R
1000
20 + 0.1Cb
300
ns
SDA, SCL signal fall time
t
F
300
20 + 0.1Cb
300
ns
Load capacitance of each bus line
Cb
400
400
pF
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