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參數資料
| 型號： | UPD77213F1-xxx-DA2 |
| 廠商： | NEC Corp. |
| 元件分類： | 數字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點數字信號處理器 |
| 文件頁數： | 32/74頁 |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77213F1-XXX-DA2 |
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Data Sheet U15203EJ3V0DS
32
μ
PD77210, 77213
7. MEMORY MAP
The
μ
PD77210 Family employs a Harvard architecture that separates the instruction memory space from the data
memory space.
7.1 Instruction Memory
7.1.1 Instruction memory map
The instruction memory space consists of 64 Kwords
×
32 bits. The area at addresses 0x8000 to 0xFFFF is a
paging area that supports a memory space of 64 Kwords or more by specifying a page by using the instruction
paging register (IPR).
The instruction ROM of the
μ
PD77213 exists in the paging area and is accessed as IPR=0x0 or 0x1.
The paging area of the
μ
PD77210 is reserved for future expansion.
Instruction RAM
(15.5 Kwords)
0xFFFF
0x8000
0x7FFF
0x0200
0x01FF
0x0000
System area
0x4000
0x3FFF
Instruction ROM
Note
(32 Kwords)
(IPR=0x0)
(IPR=0x1)
Paging area
Instruction RAM
(31.5 Kwords)
Boot-up ROM
(512 words)
0x0200
0x01FF
0x0000
0xFFFF
0x8000
0x7FFF
PD77210
μ
PD77213
μ
Paging area
(32 Kwords)
Paging area
(32 Kwords)
Boot-up ROM
(512 words)
Note
The higher 8 words of the instruction ROM (0xFFF8 to 0xFFFF) constitute system area.
Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If
these addresses are accessed, correct operation of the device is not guaranteed.
A paging area in which no IPR page exists cannot be accessed. If this kind of paging area is
accessed, correct operation of the device is not guaranteed.
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