- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379503 > UPD77213F1-xxx-DA2 (NEC Corp.) 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | UPD77213F1-xxx-DA2 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 23/74頁 |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77213F1-XXX-DA2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
Data Sheet U15203EJ3V0DS
23
μ
PD77210, 77213
2. FUNCTIONAL OUTLINE
2.1 Program Control Unit
This unit controls the execution of
μ
PD77210 Family by executing instructions and controlling branching, loop,
interrupts, clock, and standby mode.
2.1.1 CPU control
A three-stage pipeline architecture is employed so that all instructions, except branch instructions and some
others, can be executed with one system clock.
2.1.2 Interrupt control
The interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin
(INTmn) or internal peripherals (such as the serial interface, host interface, timer, and DMA controller). The interrupt
of each interrupt source can be individually enabled or disabled. In addition, multiple interrupts are also supported.
2.1.3 Loop control stack
A loop function without any hardware overhead is realized. A 4-level loop stack is provided to support multiple
loops.
2.1.4 PC stack
A 15-level PC stack that stacks the program counter supports multiple interrupts/subroutine calls.
2.1.5 Clock control
A PLL and a divider are internally provided as a clock generator so that an externally input clock is multiplied or
divided and supplied as the operating clock to the
μ
PD77210 Family. The multiple of the PLL can be set by using
external pins (PLL0 to PLL3) within a range of
×
10 to 64. The division ratio can be set by using a register in a range
of
÷
1 to 16.
The clock control register (CLKC) controls the power (ON/OFF) to the PLL, selects a clock source, controls the
output divider, and controls the output of the CLKOUT pin.
Two types of standby modes are available so that the power consumption can be reduced when the
μ
PD77210
Family is standing by.
HALT mode: Current consumption falls to several mA upon execution of the HALT instruction.
This mode is released by an interrupt or hardware reset.
STOP mode:Current consumption falls to hundreds of
μ
A
This mode is released by hardware reset or inputting a signal to CSTOP pin.
Note
upon execution of the STOP instruction.
Note
When the PLL is stopped
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD77213GJ-xxx-8EN | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| UPD7759 | ADPCM SPEECH SYNTHESIZER LSIs |
| UPD7759C | ADPCM SPEECH SYNTHESIZER LSIs |
| UPD7759GC-3BH | ADPCM SPEECH SYNTHESIZER LSIs |
| UPD77C20A | Digital Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7759C | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD780023AGB-G43-8EU-X3-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD780023AGB-G44-8EU-E3-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD780023AGC-107-8BS-A | 制造商:Renesas Electronics Corporation 功能描述:NECUPD780023AGC-107-8BS-A MASK ROM DEVIC |
| UPD780023AGK-C74-9ET-A | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。