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參數(shù)資料
| 型號： | UPD77213F1-xxx-DA2 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 31/74頁 |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77213F1-XXX-DA2 |
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Data Sheet U15203EJ3V0DS
31
μ
PD77210, 77213
6. STANDBY MODE
The
μ
PD77210 Family can be set to either of two standby modes. Each mode can be set by executing the
corresponding instruction. The power consumption can be reduced in these modes.
6.1 Halt Mode
The halt mode can be set by executing the HALT instruction. In this mode, all the functions except the clock
circuit and PLL are stopped and, therefore, the current consumption can be reduced.
The device can be released from this mode by an interrupt or hardware reset. To release the device from halt
mode by issuing an interrupt, the contents of the internal registers and memories are retained. It takes 10 to 20
system clocks to release the
μ
PD77210 Family from halt mode (if it is released by an interrupt).
When releasing the device from halt mode by using hardware reset, the external clock must be selected as the
clock source in advance that the contents of memories are retain.
In halt mode, the clock circuit of the
μ
PD77210 Family supplies the clock divided by the ratio specified by the
CLKC register as the internal system clock. The same applies to the clock output by the CLKOUT pin.
6.2 Stop Mode
Stop mode is set when a STOP instruction is executed. In this mode, supply of the clock to the internal system is
stopped.
If the PLL is stopped before stop mode is set, all the functions, including the clock circuit and PLL, are stopped.
As a result, only a leakage current flows and, therefore, the current consumption can be minimized. In this case, the
external clock must be selected as the clock source in advance.
The device is released from stop mode by a hardware reset or the CSTOP pin.
To release the device from stop mode by using the CSTOP pin, the contents of the internal registers and
memories are retained. When releasing the device from stop mode by using hardware reset, the external clock must
be selected as the clock source in advance that the contents of memories are retain.
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