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參數(shù)資料
| 型號： | UPD77210 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 35/74頁 |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77210 |
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Data Sheet U15203EJ3V0DS
35
μ
PD77210, 77213
7.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
Cautions 1. The register names shown in the above table are not reserved words in either assembler or
C. To use these names in assembler or C, therefore, the user must define them.
2. The same register is accessed regardless of whether the X memory space or Y memory
space is accessed, provided that the address is the same.
3. Different registers cannot be accessed simultaneously from the X and Y memory spaces.
Memory-Mapped Peripherals (1/3)
X/Y Memory Address
Register Name
Function
Peripheral
Name
0x3800
TSDT/SDT1
TDM serial data register/Serial data register 1
0x3801
SST1
Serial status register 1
0x3802
TSST
TDM serial status register
0x3803
TFMT
TDM frame format register
0x3804
TTXL
TDM transfer slot register (low)
0x3805
TTXH
TDM transfer slot register (high)
0x3806
TRXL
TDM receive slot register (low)
0x3807
TRXH
TDM receive slot register (high)
TSIO(SIO1)
0x3808 to 0x380F
Reserved area
Caution Do not access this area.
0x3810
ASDT/SDT2
Audio serial data register/Serial data register 2
0x3811
SST2
Serial status register 2
0x3812
ASST
Audio serial status register
ASIO(SIO2)
0x3813 to 0x381F
Reserved area
Caution Do not access this area.
0x3820
HDT
Host interface data register
0x3821
HST
Host interface status register
HIO
0x3822 to 0x383F
Reserved area
Caution Do not access this area.
0x3840
MDT
Memory data register
0x3841
MSHW
Memory I/F setup/hold width setting register
0x3842
MCST
Memory I/F control/status register
0x3843
MWAIT
Memory I/F wait register
0x3844
MIDX
Direct access index register
0x3845
MADRLI
Memory I/F input start address register (low)
0x3846
MADRHI
Memory I/F input start address register (high)
0x3847
MOFSI
Memory I/F input line offset register
0x3848
MLENI
Memory I/F input line length register
0x3849
MADRLO
Memory I/F output start address register (low)
0x384A
MADRHO
Memory I/F output start address register (high)
0x384B
MOFSO
Memory I/F output line offset register
0x384C
MLENO
Memory I/F output line length register
MIO
0x384D to 0x384F
Reserved area
Caution Do not access this area.
0x3850
PMSA0
PMT start address register 0
PMT ch0
0x3851
PMS0
PMT size register 0
0x3852
PMC0
PMT control register 0
0x3853
PMP0
PMT address pointer 0
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