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參數(shù)資料
| 型號： | UPD77210 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 27/74頁 |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77210 |
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Data Sheet U15203EJ3V0DS
27
μ
PD77210, 77213
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
supplies the clock to the
μ
PD77210 Family. The configuration of the clock generator is as illustrated below.
Stop
PLL controller
Output divider
Halt
Internal
system
clock
x m (m:10 to 64)
CLKOUT
CLKIN
÷
n (n:1 to 16)
PLL0 to PLL3
CLKC register
Peripheral bus
Standby mode
The PLL is stopped immediately after reset. The clock input from the CLKIN pin is directly supplied to the
μ
PD77210 Family internal circuitry and bootup commences. The PLL is started up in the boot routine and booting is
carried out via the PLL output clock (except in the case of non-boot or external memory boot). In the case of non-
boot or external memory boot, when booting has finished, after the PLL is started up by setting the CLKC register
from the user program, the clock source must be switched to the PLL, in which case the PLL must be locked. Note
that 300
μ
s are required between when the PLL is started up and when it is locked.
The PLL multiplication rate is specified by the external pins PLL0 to PLL3. The PLL also has two lock range
modes: 80 to 120 MHz and 120 to 160 MHz. The mode to be used is specified by the P3 pin during booting. The
CLKC register is used to control turning on/off the PLL, select the clock source (external clock/multiplied
clock/divided or non-divided output), control resetting the output divider, set the division ratio, and enable/disable
CLKOUT pin output.
When the output divider is selected, the high-level width of the clock output by the CLKOUT pin is equivalent to 1
cycle of the normal operation (which means that the clock does not have a duty factor of 50%).
In halt mode, output of the divider circuit is automatically selected as the clock source. When the divider circuit is
selected, the clock is not changed even if halt mode is set.
In stop mode, the system clock supplied to the internal circuitry is masked. Because the PLL is not stopped
automatically, it can recover from stop mode without PLL lock time. It is necessary to set the CLKC register by the
program to stop the PLL.
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