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參數(shù)資料
| 型號： | UPD754264 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大?。?/td> | 318K |
| 代理商： | UPD754264 |
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31
μ
PD754264
Table 10-1. Hardware Status After Reset (1/3)
Hardware
RESET signal generation
in the standby mode
RESET signal generation
in operation
Program counter (PC)
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11-PC8 and the
contents of address 0001H to
the PC7-PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
1000B
1000B
Data memory (RAM)
Held
Undefined
Data memory (EEPROM)
Held
Note 1
Held
Note 2
EEPROM write control register (EWC)
0
0
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Basic interval
timer/watchdog
timer
Counter (BT)
Undefined
Undefined
Mode register (BTM)
0
0
Watchdog timer enable flag (WDTM)
0
0
Timer counter
(channel 0)
Counter (T0)
0
0
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer counter
(channel 1)
Counter (T1)
0
0
Modulo register (TMOD1)
FFH
FFH
Mode register (TM1)
0
0
TOE1, TOUT F/F
0, 0
0, 0
Timer counter
(channel 2)
Counter (T2)
0
0
Modulo register (TMOD2)
FFH
FFH
High-level period setting modulo
FFH
FFH
register (TMOD2H)
Mode register (TM2)
0
0
TOE2, TOUT F/F
0, 0
0, 0
REMC, NRZ, NRZB
0, 0, 0
0, 0, 0
Notes 1.
Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode
is entered during a write operation and a RESET signal is input during a write operation.
2.
If a RESET signal is input during an EEPROM write operation, the data at that address is undefined.
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