
42
μ
PD75116H,75117H
Operation
Instruction
Group
Mne-
monic
Skip Condition
Operands
Addressing
Area
------------------------
Conforms to
referenced
instruction.
BytesMachine
Cycles
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
1
2
2
A
←
PORTn
(n = 0 to 9, 12 to 14)
XA
←
PORTn
+ 1
, PORTn (n = 4, 6, 8, 12)
PORTn
←
A
(n = 2 to 9, 12 to 14)
PORTn
+ 1
, PORTn
←
XA (n = 4, 6, 8, 12)
Set HALT Mode (PCC.2
←
1)
Set STOP Mode (PCC.3
←
1)
No Operation
RBS
←
n
(n = 0 to 3)
MBS
←
n (n = 0, 1, 2, 15)
TBR Instruction
PC
13–0
←
(taddr)
5–0
←
(taddr + 1)
PC
←
0
------------------------------------------------------------------------
TCALL Instruction
(SP – 5) (SP – 6) (SP – 3)(SP – 4)
←
PC
14–0
(SP – 2)
←
(
×
,
×
, MBE, RBE)
PC
13–0
←
(taddr)
5–0
←
(taddr + 1)
SP
←
SP – 6 PC
←
0
------------------------------------------------------------------------
Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
TBR Instruction
PC
13–0
←
(taddr)
5–0
←
(taddr + 1)
PC
←
0
------------------------------------------------------------------------
TCALL Instruction
(SP – 5) (SP – 6) (SP – 3)(SP – 4)
←
×
, PC
14–0
(SP – 2)
←
×
,
×
, MBE, RBE
PC
13–0
←
(taddr)
5–0
←
(taddr + 1)
SP
←
SP – 6, PC
14
←
0
------------------------------------------------------------------------
Other than TBR and TCALL Instruction
Execution of an instruction addressed
at (taddr) and (taddr + 1)
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
RBn
MBn
*1
HALT
STOP
NOP
IN
*1
OUT
Input/output
CPU control
SELL
taddr
*2
GETI
Special
-----------------------
Conforms to
referenced
instruction.
------------------------
3
3
4
*10
1
*10
1
------------------------
4
3
3
Remarks
Shading indicates a part compatible with the
μ
PD75117H.
*
1.
When executing the IN/OUT instruction, <MBE = 0> or <MBE = 1, MBS = 15> must be set.
2.
The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction.