參數(shù)資料
型號(hào)： UPD75117HGK
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 31/66頁(yè)
文件大小： 472K
代理商： UPD75117HGK
31
μ
PD75116H,75117H
RESET Input in Standby
Mode
Table 8-1 Status of Each Hardware after Resetting (1/2)
RESET Input during
Operation
Low-order 6 bits of
program memory address
0000H are set in PC
13
to PC
8
and the contents of address
0001H are set in PC
7
to PC
0
.
PC
14
*1
is set to 0.
Undefined
0
0
Sets program memory
address 000H bit 6 and bit
7 to RBE and MBE,
respectively.
Undefined
Undefined
Undefined
Undefined
0, 0
Low-order 6 bits of program
memory address 0000H are
set in PC
13
to PC
8
and the
contents of address 0001H
are set in PC
7
to PC
0
. PC
14
*1
is set to 0.
Undefined
0
0
FFH
0
0, 0
Held
0
0
0
Held
0
0
Sets program memory
address 000H bit 6 and bit 7
to RBE and MBE, respec-
tively.
Undefined
Undefined
Held
*2
Held
0, 0
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Serial interface
Clock generator,
clock output
circuit
Counter (BT)
Mode register (BTM)
Counter (Tn)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOFn
Shift register (SIO)
Mode register (SIOM)
Processor clock control register (PCC)
Clock output mode register (CLOM)
Undefined
0
0
FFH
0
0, 0
Undefined
0
0
0
Hardware
Program counter (PC)
Carry flag (CY)
Skip flag (SK0 to SK2)
PSW
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Stack bank selection register (SBS)
*1
Data memory (RAM)
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
* 1.
Compatible with the
μ
PD75117H only.
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
2.
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