
57
μ
PD75108F,75112F,75116F
Other than below
Ports 0,1,TI0, 1, RESET
Internal pull-up resistor
Ports 12 to 14
Open–drain
X1, X2
Other than below
Ports 0,1,TI0, 1, RESET
X1, X2
V
DD
= 4.5 to 5.0 V, I
OH
= –1 mA
I
OH
= –100
μ
A
Ports 0, 2 to 9, I
OL
= 15 mA
V
DD
= 4.5 to 5.0 V
Ports 12 to 14, I
OL
= 10 mA
V
DD
= 4.5 to 5.0 V, I
OL
= 1.6 mA
I
OL
= 400
μ
A
Other than below
V
IN
= V
DD
X1, X2
V
IV
= 10 V
Ports 12 to 14 (open-drain)
Except X1, X2
V
IN
= 0 V
X1, X2
V
OUT
= V
DD
Other than below
V
OUT
= 10 V
Ports 12 to 14 (open-drain)
V
DD
= 4.5 to 5.0 V
Ports 12 to 14
V
DD
= 4.5 to 5.0 V
*2
V
DD
= 2.8 to 3.3 V
*3
V
DD
= 4.5 to 5.0 V
V
DD
= 2.8 to 3.3 V
STOP mode, V
DD
= 2.8 to 3.3 V
DC CHARACTERISTICS (Ta = –40 to +60
°
C, V
DD
= 2.8 to 5.0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IH1
V
IH2
V
IH3
V
IH4
Input voltage high
V
IL1
V
IL2
V
IL3
Input voltage low
V
OH
Output voltage high
V
OL
Output voltage low
I
LIH1
I
LIH2
I
LIH3
Input leakage
current high
Input leakage
current low
I
LIL1
I
LIL2
I
LOH1
I
LOH2
Output leakage
current high
Output leakage
current low
V
OUT
= 0 V
I
LOL
Internal pull-up
resistor
(mask option)
R
L
I
DD1
4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF
HALT
mode
I
DD2
I
DD3
Supply current
*1
–3
μ
A
*
1.
Excluding current flowing in the internal pull-up resistors and comparator circuit.
2.
When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode.
3.
When the PCC register is set to 0000 for operation in the low-speed mode.
0.7 V
DD
V
DD
V
0.8 V
DD
V
DD
V
0.7 V
DD
V
DD
V
0.7 V
DD
10
V
V
DD
– 0.5
V
DD
V
0
0.3 V
DD
V
0
0.2 V
DD
V
0
0.4
V
V
DD
– 1.0
V
V
DD
– 0.5
V
0.35
2.0
V
0.35
2.0
V
0.4
V
0.5
V
3
μ
A
20
μ
A
20
μ
A
–3
μ
A
–20
μ
A
3
μ
A
20
μ
A
15
40
70
k
10
80
k
3
9
mA
0.55
1.5
mA
600
1800
μ
A
200
600
μ
A
0.1
10
μ
A