
37
μ
PD75108F,75112F,75116F
A
A
reg
rp1
@HL
mem
reg
rp'
reg, #n4
@HL, #n4
A, @HL
XA, @HL
A, reg
XA, rp'
CY
CY
CY
CY
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
mem.bit
fmem.bit
pmem.@L
@H + mem.bit
fmem.bit
pmem.@L
@H + mem.bit
Operands
Operation
Instruction
Group
Mne-
monic
Bytes
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Machine
Cycles
CY
←
A
0
, A
3
←
CY, A
n–1
←
A
n
A
←
A
reg
←
reg + 1
rp1
←
rp1 + 1
(HL)
←
(HL) + 1
(mem)
←
(mem) + 1
reg
←
reg – 1
rp'
←
rp' – 1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp'
CY
←
1
CY
←
0
Skip if CY = 1
CY
←
CY
(mem.bit)
←
1
(fmem.bit)
←
1
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
←
1
(H + mem
3–0
.bit)
←
1
(mem.bit)
←
0
(fmem.bit)
←
0
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
←
0
(H + mem
3–0
.bit)
←
0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (pmem
7–2
+ L
3–2
.bit (L
1–0
)) = 1
Skip if (H + mem
3–0
.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (pmem
7–2
+ L
3–2
.bit (L
1–0
)) = 0
Skip if (H + mem
3–0
.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
7–2
+ L
3–2
.bit (L
1–0
))
= 1 and clear
Skip if (H + mem
3–0
.bit)
= 1 and clear
Addressing
Area
Skip Condition
reg = 0
rp1 = 00H
(HL) = 0
(mem) = 0
reg = FH
rp' = FFH
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
XA = rp'
CY = 1
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
1
2
1 + S
1 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1
1
1 + S
1
2
2
2
2
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
RORC
*1
*3
*1
*1
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
Accumulator
manipulation
NOT
INCS
Increment
/decrement
DECS
SKE
Comparison
SET1
CLR1
SKT
NOT1
Carry flag
manipulation
SET1
Memory bit
manipulation
CLR1
SKT
SKF
SKTCLR