
27
μ
PD75108F,75112F,75116F
6.
INTERRUPT FUNCTION
The
μ
PD75116F has 7 interrupt sources. Multiple interrupts with priority is are also possible.
Two test sources are also provided. The test sources are edge detection testable inputs.
Table 6-1 Interrupt Sources
INTBT (standard time interval signal from
basic interval timer)
INT4
(both rising edge and falling edge
detection)
INT0
INT1
INTT0
(match signal from timer/event
counter# 0 or TI0 input edge detection)
INTT1
(match signal from timer/event
counter# 1 or TI1 input edge detection)
INT2
*2
(rising edge detection)
INT3
*2
(rising edge detection)
Vector Interrupt Request
Signal
(Vector Table Address)
(rising edge and falling edge
detection selection)
Internal
External
1
2
Interrupt Order
*1
Internal/External
Interrupt Source
External
External
VRQ1
(0002H)
VRQ3
(0006H)
INTSIO (serial data transfer end signal)
Internal
Internal/external
Internal/external
3
4
5
VRQ4
(0008H)
VRQ5
(000AH)
VRQ2
(0004H)
External
Testable input signal
(Set IRQ2 and IRQ3)
*
1.
The interrupt order is the priority order when multiple interrupt requests are generated simultaneously.
2.
INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt
sources, but do not generate vector interrupts.
The
μ
PD75116F interrupt control circuit has the following functions:
Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IE
×××
)
and interrupt master enable flag (IME).
Arbitrary setting of interrupt start address.
Multiple interruption function by which priority can be specified using the interrupt priority selection register
(IPS).
Interrupt request flag (IRQ
×××
) test function (interrupt generation confirmation by software possible).
Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).