參數(shù)資料
型號： UPD75104GF
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁數(shù)： 31/70頁
文件大?。?/td> 535K
代理商： UPD75104GF
μ
PD75104, 75106, 75108
31
8.
RESET FUNCTION
The reset (
RES
) signal generator circuit is configured as shown in Figure 8-1.
RESET
SWB
SWA
Power-ON
reset
generator
circuit
Internal reset signal
(RES)
Power-ON
flag (PONF)
Execution of bit
manipulation
instruction*
I
*: PONF cannot be set to 1 by SET1 instruction.
Fig. 8-1 Reset Signal Generator Circuit
The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse
can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK
OPTION SELECTION.)
The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs.
8-2 and 8-3, respectively.
Supply voltage
0 V
Internal reset signal
(RES)
Wait*
(approx. 31.3 ms: 4.19 MHz)
HALT mode
Operation mode
Internal reset operation
*: The wait time does not include the time required after the
RES
signal has been generated until the
oscillation starts.
Fig. 8-2 Reset by Power-ON Reset Circuit
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