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參數(shù)資料
| 型號(hào)： | UPD750004GBA-XXX-3BS-MTX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 9/86頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
15
Data Sheet U10738EJ3V2DS
4.2
SETTING OF THE STACK BANK SELECTION REGISTER (SBS)
The Mk
Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Fig. 4-1 shows the register
configuration.
The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk
Ι mode,
initialize the register to 100
×BNote at the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to
000
×BNote.
Note Specify the desired value in
×.
Fig. 4-1
Stack Bank Selection Register Format
Caution The CPU operates in Mk
Ι mode after the RESET signal is issued, because bit 3 of SBS is set to 1.
Set bit 3 of SBS to 0 (Mk
ΙΙ mode) to use the CPU in Mk ΙΙ mode.
SBS0
SBS1
SBS2
SBS3
0
1
2
3
F84H
Address
SBS
Symbol
0
1
Memory bank 0
Memory bank 1
Other settings are inhibited.
0
1
Mk
ΙΙ mode
Mk
Ι mode
Mode switching designation
Bit 2 must be set to 0.
Stack area designation
0
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