參數(shù)資料
型號： UPD750004GBA-XXX-3BS-MTX
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù)： 60/86頁
文件大?。?/td> 626K
代理商： UPD750004GBA-XXX-3BS-MTX
PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
61
Data Sheet U10738EJ3V2DS
Typ.
Max.
250
1000
Unit
ns
Min.
1300
3800
tKCY1/2 - 50
tKCY1/2 - 150
150
500
400
600
0
Conditions
VDD = 2.7 to 5.5 V
RL = 1 k
VDD = 2.7 to 5.5 V
CL = 100 pFNote 2
Symbol
tKCY1
tKL1,
tKH1
tSIK1
tKSI1
tKSO1
Parameter
SCK cycle time
SCK high/low level
width
SINote 1 setup time
(referred to SCK
↑)
SINote 1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SONote 1 output
SERIAL TRANSFER OPERATION
Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (TA = -40 to +85
°C, VDD = 2.2 to 5.5 V)
Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2. RL is the resistance of the SO output line load, while CL is the capacitance.
Two-wire and three-wire serial I/O modes (SCK: External clock input): (TA = -40 to +85
°C, VDD = 2.2 to 5.5 V)
Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.
2. RL is the resistance of the SO output line load, while CL is the capacitance.
Typ.
Max.
300
1000
Unit
ns
Min.
800
3200
400
1600
100
150
400
600
0
Conditions
VDD = 2.7 to 5.5 V
RL = 1 k
VDD = 2.7 to 5.5 V
CL = 100 pFNote 2
Symbol
tKCY2
tKL2,
tKH2
tSIK2
tKSI2
tKSO2
Parameter
SCK cycle time
SCK high/low level
width
SINote 1 setup time
(referred to SCK
↑)
SINote 1 hold time
(referred to SCK
↑)
Delay time from SCK
↓
to SONote 1 output
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