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參數(shù)資料
| 型號： | UPD750004GBA-XXX-3BS-MTX |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 21/86頁 |
| 文件大?。?/td> | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
26
Data Sheet U10738EJ3V2DS
6.6
CLOCK TIMER
The
PD750008 contains one channel for a clock timer. The clock timer provides the following functions:
Sets the test flag (IRQW) with a 0.5 sec interval. The standby mode can be released by IRQW.
The 0.5 second interval can be generated from either the main system clock (4.194304 MHz) or subsystem clock
(32.768 kHz).
The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for
program debugging, testing, etc.
Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be
used for beep and system clock frequency trimming.
The frequency divider circuit can be cleared so that a zero-second start of the clock can be made.
Fig. 6-5
Clock Timer Block Diagram
( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
P23/BUZ
Internal bus
8
Selector
From the
clock
generator
fX
128
(32.768 kHz)
fXT
(32.768 kHz)
Selector
Frequency divider
Selector
INTW
IRQW
set signal
2 Hz
0.5 sec
WM7
0
WM5
WM4
WM3
WM2
WM1
WM0
P23 output
latch
Bit 2 of PMGB
PORT2.3
Output buffer
Clear
fW
(32.768 kHz)
Bit test instruction
Port 2 input/
output mode
WM
(4 kHz) (2 kHz)
fw
2
7
(256 Hz: 3.91 ms)
fw
2
14
fw
2
3
fw
2
4
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