參數(shù)資料
型號(hào)： UPD72042A
廠商： NEC Corp.
英文描述： LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述： LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制
文件頁(yè)數(shù)： 6/92頁(yè)
文件大?。?/td> 541K
代理商： UPD72042A
μ
PD72042A, 72042B
6
DATA SHEET S13990EJ2V0DS00
1. PIN FUNCTIONS
1.1 PIN FUNCTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin
Note
SCK
SI (SIO)
SO (NC)
IRQ
C/D
XI
XO
GND
BUS–
BUS+
AV
DD
SEL
CS
I/O
Note
Input
Input (I/O)
Output
(none)
Output
Input
–
–
I/O
–
Input
Input
Function
Serial clock input pin for CPU interface
Serial data pin for CPU interface. (This pin
functions as an input pin when 3-wire serial
I/O mode is selected, or as an I/O pin when
2-wire serial I/O mode is selected.)
Serial data output pin for CPU interface. (The
pin functions as an output when 3-wire serial I/O
mode is selected. When 2-wire serial I/O mode
is selected, the pin is left open.)
Output pin for making an interrupt request to the
CPU. When a return code or a program crash is
detected, a high-level signal is output on this pin
for at least 8
μ
s.
Input pin used to select control mode or data
read/write mode. When this pin is driven high,
internal register address setting and data read/
write are enabled. When the mode changes, the
serial clock counter is reset.
Pins for connecting a system clock resonator. A
6- or 6.29-MHz crystal or ceramic resonator
must be used. The accuracy of the frequency is
as follows;
Mode 0, 1:
±
1.5%
Ground pin
I/O pins connected to the IEBus bus
Main power supply pin for the IEBus bus driver/
receiver. When used, this pin must be tied to
V
DD
.
Input pin used to select either 3- or 2-wire serial
I/O mode. A high-level signal on this pin selects
3-wire serial I/O mode. A low-level signal on this
pin selects 2-wire serial I/O mode.
Chip select pin. When this pin is driven low, the
serial interface is enabled. When this pin is
driven high, the SO pin becomes high-imped-
ance, and the serial clock counter is reset.
When reset
[for both hardware
and software]
Input
Input
High-impedance
Low level
Input
When reset by
hardware (Oscil-
lation stopped)
XI = GND
XO = High level
When reset by
software (Oscil-
lation continued)
–
High-impedance
–
Input
Input
I/O format
Note
CMOS input
CMOS input
(CMOS I/O)
CMOS output
(none)
CMOS output
CMOS input
–
–
–
–
CMOS input
CMOS input
Note
Parentheses indicate the state corresponding to two-wire serial I/O mode.
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