參數(shù)資料
型號(hào)： uPD70F3102GJ-33-UEN
廠商： NEC Corp.
英文描述： 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： 32-/16-BIT單片機(jī)
文件頁(yè)數(shù)： 61/82頁(yè)
文件大?。?/td> 476K
代理商： UPD70F3102GJ-33-UEN
Preliminary Data Sheet U13844EJ2V0DS00
61
μ
PD70F3102-33
(h) DMA flyby transfer timing (external I/O
→
DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
↓
)
<24>
t
SWK
15
ns
WAIT hold time (from CLKOUT
↓
)
<25>
t
HKW
2
ns
IORD low-level width
<32>
t
WRDL
(2 + w
RH
+ w
DA
+ w
F
+ w) T – 10
ns
IORD high-level width
<33>
t
WRDH
T – 10
ns
Delay time from address to IORD
↑
<34>
t
DARD
0.5T – 10
ns
Delay time from IORD
↑
to address
<35>
t
DRDA
(0.5 + i) T – 10
ns
Row address setup time
<56>
t
ASR
(0.5 + w
RP
) T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
) T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(1.5 + w
DA
+ w
F
) T – 10
ns
Read/write cycle time
<60>
t
RC
(3 + w
RP
+ w
RH
+ w
DA
+ w
F
+ w) T – 10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
) T – 10
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
+ w
F
) T – 10
ns
Column address read time for RAS
<64>
t
RAL
(2 + w
CP
+ w
DA
+ w
F
+ w) T – 10
ns
CAS pulse width
<65>
t
CAS
(1 + w
DA
+ w
F
) T – 10
ns
CAS to RAS precharge time
<66>
t
CRP
(1 + w
RP
) T – 10
ns
CAS hold time
<67>
t
CSH
(2 + w
RH
+ w
DA
+ w
F
+ w) T – 10
ns
CAS precharge time
<71>
t
CPN
(2 + w
RP
+ w
RH
+ w) T – 10
ns
RAS column address delay time
<76>
t
RAD
(0.5 + w
RH
) T – 10
ns
RAS to CAS delay time
<77>
t
RCD
(1 + w
RH
+ w) T – 10
ns
CAS precharge time
<81>
t
CP
(0.5 + w
CP
+ w) T – 10
ns
High-speed page mode cycle time
<82>
t
PC
(2 + w
CP
+ w
DA
+ w
F
+ w) T – 10
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2.5 + w
CP
+ w
DA
+ w) T – 10
ns
WE hold time (from CAS
↓
)
<85>
t
WCH
(1 + w
DA
) T – 10
ns
WE read time (to RAS
↑
)
<88>
t
RWL
w
CP
= 0
(1.5 + w
DA
+ w) T – 10
ns
WE read time (to CAS
↑
)
<89>
t
CWL
w
CP
= 0
(1 + w
DA
+ w) T – 10
ns
WE pulse width
<92>
t
WP
w
CP
= 0
(1 + w
DA
+ w) T – 10
ns
RAS pulse width
<94>
t
RASP
(2.5 + w
RH
+ w
DA
+ w
F
+ w) T – 10
ns
Remarks 1.
T = t
CYK
2.
w: Number of waits due to WAIT
3.
w
RH
: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4.
w
DA
: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5.
w
RP
: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6.
w
CP
: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
7.
w
F
: Number of waits inserted to source-side access during DMA flyby transfer.
8.
i: Number of idle states inserted when a write cycle follows the read cycle.
9.
n = 0 to 7
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