參數(shù)資料
型號(hào)： uPD70F3102GJ-33-UEN
廠商： NEC Corp.
英文描述： 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： 32-/16-BIT單片機(jī)
文件頁(yè)數(shù)： 59/82頁(yè)
文件大小： 476K
代理商： UPD70F3102GJ-33-UEN
Preliminary Data Sheet U13844EJ2V0DS00
59
μ
PD70F3102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page)
→
external I/O transfer) (2/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output buffer turn-off delay time
(from OE
↑
)
<78>
t
OEZ
0
ns
Output buffer turn-off delay time
(from CAS
↑
)
<79>
t
OFF
0
ns
CAS precharge time
<81>
t
CP
(0.5 + w
CP
) T – 10
ns
High-speed mode cycle time
<82>
t
PC
(2 + w
CP
+ w
DA
+ w
F
+ w)
T – 10
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2.5 + w
CP
+ w
DA
+ w
F
+
w) T – 10
ns
RAS pulse width
<94>
t
RASP
(2.5 + w
RH
+ w
DA
+ w
F
+
w) T – 10
ns
Off-page
<96>
t
OCH1
(2.5 + w
RP
+ w
RH
+
w
DA
+ w
F
+ w) T – 10
ns
Hold time from
OE to CAS
(from CAS
↑
)
On-page
<97>
t
OCH2
(1.5 + w
CP
+ w
DA
+ w
F
+
w) T – 10
ns
Delay time from DMAAKm
↓
to
CAS
↓
<105>
t
DDACS
(1.5 + w
RH
) T – 10
ns
Delay time from IOWR
↓
to CAS
↓
<106>
t
DRDCS
(1 + w
RH
) T – 10
ns
Remarks 1.
T = t
CYK
2.
w: Number of waits due to WAIT
3.
w
CP
: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4.
w
DA
: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5.
w
RH
: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6.
w
RP
: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
7.
w
F
: Number of waits inserted to source-side access during DMA flyby transfer
8.
m = 0 to 3
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