
1999
DATA SHEET
V832
TM
32-BIT MICROPROCESSOR
MOS INTEGRATED CIRCUIT
μ
PD705102
DESCRIPTION
The
μ
PD705102 (V832) is a 32-bit RISC microprocessor for embedded control applications, with a high-
performance 32-bit V830
TM
processor core and many peripheral functions such as a SDRAM/ROM controller, 4-
channel DMA controller, real-time pulse unit, serial interface, interrupt controller, and power management.
In addition to high interrupt response speed and optimized pipeline structure, the V832 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore can provide high performance in multimedia systems such as Internet/intra-net systems, car
navigation systems, digital still cameras, and color faxes.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V832 User’s Manual — Hardware:
V830 Family
TM
User’s Manual — Architecture: U12496E
U13577E
Document No. U13675EJ2V1DS00 (2nd edition)
Date Published July 1999 N CP(K)
Printed in Japan
FEATURES
CPU function
V830-compatible instructions
Instruction cache:
Instruction RAM:
Data cache:
Data RAM:
Minimum number of instruction
execution cycles:
Number of general purpose
registers:
Memory space and I/O space:
Interrupt/exception processing function
Non-maskable: External input:
Maskable:
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
1 cycle
32 bits
×
32
4 Gbytes each
1
8 (of which 4 are
multiplexed with
internal sources)
External input:
Internal source: 11 types
Bus control function
Wait control function
Memory access control function
DMA controller: 4 channels
Serial interface function
Asynchronous serial interface (UART): 1 channel
Clocked serial interface (CSI):
Dedicated baud rate generator (BRG): 1 channel
Timer/counter function
16-bit timer/event counter: 1 channel
16-bit interval timer:
Port function: 21 I/O ports
Clock generation function: PLL clock synthesizer (6
×
or
8
×
multiplication)
Standby function: HALT, STOP, and power manage-
ment modes
Debug function
Debug-dedicated synchronous serial
interface:
Trace-dedicated interface:
1 channel
1 channel
1 channel
1 channel
The mark shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.