參數(shù)資料
型號(hào): UPD703100GJ-40-8EU
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁(yè)數(shù): 92/132頁(yè)
文件大小: 1174K
代理商: UPD703100GJ-40-8EU
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Preliminary Data Sheet U14168EJ2V0DS00
92
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
)
<24>
t
SWK
10
ns
WAIT hold time (from CLKOUT
)
<25>
t
HKW
2
ns
Data input setup time (to CLKOUT
)
<26>
t
SKID
10
ns
Data input hold time (from CLKOUT
)
<27>
t
HKID
2
ns
Data output delay time from OE
<37>
t
DRDOD
(0.5 + i) T – 10
ns
Row address setup time
<56>
t
ASR
(0.5 + w
RP
) T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
) T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(1.5 + w
DA
+ w) T – 10
ns
Read/write cycle time
<60>
t
RC
(3 + w
RP
+ w
RH
+ w
DA
+ w)
T –
10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
) T – 5
ns
RAS pulse time
<62>
t
RAS
(2.5 + w
RH
+ w
DA
+ w)
T – 10
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
+ w) T – 10
ns
Column address read time for RAS
<64>
t
RAL
(2 + w
DA
+ w) T – 10
ns
CAS pulse width
<65>
t
CAS
(1 + w
DA
+ w) T – 10
ns
CAS-RAS precharge time
<66>
t
CRP
(1 + w
RP
) T – 10
ns
CAS hold time
<67>
t
CSH
(2 + w
RH
+ w
DA
+ w)
T – 10
ns
WE setup time
<68>
t
RCS
(2 + w
RP
+ w
RH
) T – 10
ns
WE hold time (from RAS
)
<69>
t
RRH
0.5T – 10
ns
WE hold time (from CAS
)
<70>
t
RCH
T – 10
ns
CAS precharge time
<71>
t
CPN
(2 + w
RP
+ w
RH
) T – 5
ns
Output enable access time
<72>
t
OEA
(2 + w
RP
+ w
RH
+ w
DA
+ w)
T – 20
ns
RAS access time
<73>
t
RAC
(2 + w
RH
+ w
DA
+ w)
T – 20
ns
Access time from column address
<74>
t
AA
(1.5 + w
DA
+ w) T – 20
ns
CAS access time
<75>
t
CAC
(1 + w
DA
+ w) T – 20
ns
Remarks 1.
T = t
CYK
2.
w: the number of waits due to WAIT.
3.
w
RP
: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
w
RH
: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6.
i: the number of idle states that are inserted when a write cycle follows a read cycle.
相關(guān)PDF資料
PDF描述
UPD703100-33 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703100-40 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703100AF1-33-FA1 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703100AF1-40-FA1 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703100A-40 V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
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參數(shù)描述
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