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參數(shù)資料
| 型號(hào)： | UPD64 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION |
| 中文描述： | 4位單片機(jī)的紅外遙控傳輸 |
| 文件頁數(shù)： | 9/68頁 |
| 文件大?。?/td> | 301K |
| 代理商： | UPD64 |
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9
μ
PD63, 63A, 64
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 10 Bits
Refers to the binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Organization
PC9
PC0
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC
The program counter contains the address of the instruction that should be executed next. Normally, the counter
contents are automatically incremented in accordance with the instruction length (byte count) each time an
instruction is executed.
However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump
destination address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
When reset, the value of the program counter becomes “000H”.
2.2 Stack Pointer (SP): 1 Bit
Refers to the 1-bit register which holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented
when the return instruction (RET) is executed.
When reset, the stack pointer contents are cleared to “0”.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up thus a system reset
signal is generated and the PC becoming “000H”.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 10 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The low-order 8 bits are arranged in the RF of the data memory as a dual-function RAM. The register holds
the ASR value even after the RET is executed.
When reset, it holds the previous data (undefined when turning on the power).
Caution If the RF is accessed as the data memory, the high-order 2 bits of the ASR become undefined.
Figure 2-2. Address Stack Register Organization
ASR9
ASR8
ASR7
ASR6
ASR5
ASR4
ASR3
ASR2
ASR1
ASR0
ASR
RF
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