
60
μ
PD63, 63A, 64
Item
μ
PD63
512
×
10 bits
32
×
4 bits
1 level (multiplexed with RF of RAM)
μ
PD63A
768
×
10 bits
μ
PD64
μ
PD6134
1002
×
10 bits
μ
PD6600A
512
×
10 bits
32
×
5 bits
3 levels
(multiplexed with RAM)
8
×
4 = 32 keys
Read by left shift
instruction
Output
Ceramic oscillation
ROM capacity
RAM capacity
Stack
1002
×
10 bits
Key matrix
S
0
(S-IN) input
8
×
6 = 48 keys
Read by P
01
register (with function to release standby mode)
S
1
/LED (S-OUT)
Clock frequency
I/O (with function to release standby mode)
Ceramic oscillation
f
X
= 2.4 to 8 MHz
f
X
= 2.4 to 4 MHz (with POC circuit)
f
X
= 300 kHz to 1 MHz f
X
= 400 to 500 kHz
f
X
= 300 to 500 kHz
(with POC circuit)
f
X
/8, f
X
/16
Timer
Clock
Count start
f
X
/64, f
X
/128
Writing count value
f
X
/8
Writing count value
and P1 register value
f
X
/8, f
X
Carrier
Frequency
f
X
/8, f
X
/64, f
X
/96 (timer clock: f
X
/64)
f
X
/16, f
X
/128, f
X
/192 (timer clock: f
X
/128)
No carrier
f
X
, f
X
/8, f
X
/12
(timer clock: f
X
/8)
f
X
/2, f
X
/16, f
X
/24
(timer clock: f
X
/16)
No carrier
Output start
Synchronized with timer
Not synchronized
with timer
16
μ
s (f
X
= 500 kHz)
Provided
Provided
n = 0 to F
HALT/STOP mode
set by P1 register
value
HALT instruction
executed regardless
of status of F
Provided
Instruction execution time
Relative branch instruction
Left shift instruction
“MOV Rn, @RO” instruction
Standby mode
(HALT instruction)
8
μ
s (f
X
= 8 MHz)
None
None
n = 1 to F
HALT mode for timer only.
STOP mode for only releasing K
I
(K
I/O
high-level output or K
I/O0
high-level output)
HALT instruction not executed when F = 1
8
μ
s (f
X
= 1 MHz)
Relation between HALT
instruction execution and
status flag (F)
Reset function by charging/
discharging capacitor
POC circuit
None
Mask option
Low level output to RESET pin on detection
Provided (low-voltage
detection circuit)
Low level output to
S-OUT pin on detection
Pull-down resistor
Variable duty
Hang-up detection
V
DD
= 2.2 to 3.6 V
Mask option
POC circuit only
(Circuits other than POC circuit are set by software.)
Supply voltage
V
DD
= 1.8 to 3.6 V
V
DD
= 2.2 to 3.6 V (with POC circuit)
T
A
= –40 to +85
°
C
T
A
= –20 to +70
°
C (with POC circuit)
20-pin plastic SOP
Operating temperature
T
A
= –20 to +70
°
C
Package
20-pin plastic 20-pin plastic SOP
SOP
20-pin plastic
SSOP
μ
PD61P34B
20-pin plastic SOC
20-pin plastic shrink
DIP
One-time PROM model
μ
PD6P4B
μ
PD61P24
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN
μ
PD63 SUBSERIES AND OTHER
SUBSERIES