參數(shù)資料
型號(hào)： UPD6451A
英文描述： UPD6451A Data Sheet | Data Sheet[12/1995]
中文描述： UPD6451A數(shù)據(jù)表|數(shù)據(jù)表[12/1995]
文件頁(yè)數(shù)： 17/68頁(yè)
文件大小： 301K
代理商： UPD6451A
17
μ
PD63, 63A, 64
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0000 0011B.
Table 3-4. Control Register 0 (P3)
Bit
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Name
—
—
DP (Data pointer) TCTL
CARY
MOD
1
MOD
0
DP
9
DP
8
Set
0
Fixed
Fixed
0
0
1/1
ON
Refer to
Table 3-5
.
value
1
to “0”
to “0”
1
1
1/2
OFF
When reset
0
0
0
0
0
0
1
1
b
0
, b
1
: These bits specify the carrier frequency and duty ratio of the REM output.
b
2
: This bit specifies the availability of the carrier of the frequency specified by b
0
and b
1
.
“0” = ON (with carrier); “1” = OFF (without carrier; high level)
b
3
: This bit changes the carrier frequency and the timer clock’s frequency division ratio.
“0” = 1/1 (carrier frequency: the specified value of b
0
and b
1
; timer clock: f
X
/64)
“1” = 1/2 (carrier frequency: half of the specified value of b
0
and b
1
; timer clock: f
X
/128)
Table 3-5. Timer Clock and Carrier Frequency Setup
b
3
b
2
b
1
b
0
Timer Clock
Carrier Frequency (Duty Ratio)
0
0
0
0
f
X
/64
f
X
/8 (Duty 1/2)
0
1
f
X
/64 (Duty 1/2)
1
0
f
X
/96 (Duty 1/2)
1
1
f
X
/96 (Duty 1/3)
1
×
×
Without carrier (high level)
0
0
0
0
f
X
/128
f
X
/16 (Duty 1/2)
0
1
f
X
/128 (Duty 1/2)
1
0
f
X
/192 (Duty 1/2)
1
1
f
X
/192 (Duty 1/3)
1
×
×
Without carrier (high level)
b
4
and b
5
: These bits specify the high-order 2 bits (DP
8
and DP
9
) of ROM’s data pointer.
Remark
×
: don’t care
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