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參數(shù)資料
| 型號(hào)： | UPD44323362 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 中文描述： | 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 252K |
| 代理商： | UPD44323362 |
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Data Sheet M16379EJ4V0DS
μ
PD44323362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is moved
into the run-test/idle or the various data register state. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE
instruction at power-up whenever the controller is placed in test-logic-reset state.
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test
data to be passed through the RAMs TAP to another device in the scan chain with as little delay as
possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the
controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The
register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state.
The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs
I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins
when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the
boundary register. The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input
or I/O at the bump and the third column is the bump number
Bypass register
ID register
Boundary register
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
70
bit
ID Register Definition
ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no. ID [0] fix bit
XXXX
0000 0000 0011 1100
00000010000
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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