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參數(shù)資料
| 型號： | UPD44323362 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 中文描述： | 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 252K |
| 代理商： | UPD44323362 |
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10
Data Sheet M16379EJ4V0DS
μ
PD44323362
Read and Write Cycle
Parameter
Symbol
MIN.
MAX.
Unit
Note
Clock cycle time
t
KHKH
4.0
–
ns
Clock phase time
t
KHKL /
t
KLKH
1.5
–
ns
Setup times
Address
t
AVKH
0.5
–
ns
Write data
t
DVKH
Write enable
t
WVKH
Chip select
t
SVKH
Hold times
Address
t
KHAX
0.5
–
ns
Write data
t
KHDX
Write enable
t
KHWX
Chip select
t
KHSX
Clock access time
t
KHQV
–
2.0
ns
1
K high to Q change
t
KHQX
0.5
–
ns
2
/G low to Q valid
t
GLQV
–
2.0
ns
1
/G low to Q change
t
GLQX
0.5
–
ns
2
/G high to Q High-Z
t
GHQZ
1.0
2.0
ns
2
K high to Q High-Z (/SW)
t
KHQZ
1.0
2.5
ns
2
K high to Q High-Z (/SS)
t
KHQZ2
1.0
2.5
ns
2
K high to Q Low-Z
t
KHQX2
0.7
–
ns
/G high Pulse width
t
GHGL
4.0
–
ns
3
/G high to K high
t
GHKH
1.0
–
ns
3
K high to /G low
t
KHGL
2.5
–
ns
3
Sleep mode recovery
t
ZZR
2
–
Cycle
4
Sleep mode enable
t
ZZE
–
2
Cycle
4
Notes
1.
See figure. (V
TT
= 0.75 V, RQ = 250
)
2.
See figure. (V
TT
= 0.75 V, RQ = 250
)
DQ (Output)
Zo = 50
50
V
TT
3.
Controlled impedance push-pull output buffer mode only.
DQ (Output)
5 pF
50
V
TT
4.
/SS must be 'high' before sleep mode entry.
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