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CHAPTER 6 EXCEPTION PROCESSING
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(2) Operating mode
The operating mode is specified by KSU bit in the Status register when both the exception level and error level
are normal (0).
(3) Exception/error levels
The operation enters Kernel mode when either EXL bit or ERL bit in the Status register is set to 1. Returning
from an exception resets the exception level to normal (0) (for details, see Chapter 27).
The registers that retain address, cause, and status information during exception processing are described in
6.3
EXCEPTION PROCESSING REGISTERS
. For a description of the exception process, see
6.4 DETAILS OF
EXCEPTIONS
.
6.2 PRECISION OF EXCEPTIONS
V
R
4102 exceptions are logically precise; the instruction that causes an exception and all those that follow it are
aborted and can be re-executed after servicing the exception. When succeeding instructions are killed, exceptions
associated with those instructions are also killed. Exceptions are not taken in the order detected, but in instruction
fetch order.
There is a special case in which the V
R
4102 processor may not be able to restart easily after servicing an
exception. When a cache data parity error exception occurs on a load with a cache hit, the V
R
4102 processor does
not prevent the cache data (with erroneous parity) from being written back into the register file during the WB stage.
The exception is still precise, since both the EPC and CacheError registers are updated with the correct virtual
address pointing to the offending load instruction, and the exception handler can still determine the cause of
exception and its origin. The program can be restarted by rewriting the destination register - not automatically,
however, as in the case of all the other precise exceptions where no status change occurs.