參數(shù)資料
型號: UPD17P207GF-001-3B9
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, PLASTIC, QFP-80
文件頁數(shù): 2/34頁
文件大?。?/td> 311K
代理商: UPD17P207GF-001-3B9
PD17P207
8
(cont’d)
Pin No.
Symbol
Function
Output Type
On Reset
Port 1A or serial interface.
Port 1A and serial interface are switched by SIOEN of the
register file.
58
P1A0/SCK
P1A0 to P1A2
3-bit I/O port
CMOS,
Input
59
P1A1/SO
Enabling setting of inputs or outputs of 3 bits
push-pull
(Grouped I/O)
60
P1A2/SI
SCK, SO, SI
SCK: Serial clock I/O
SO:
Serial data output
SI:
Serial data input
61
REM
Signal output to an infrared remote controller.
CMOS,
Low-level
Active-high output
push-pull
output
62
VDD
Positive power supply.
63
XIN
These pins are connected to a 4-MHz ceramic or crystal
64
XOUT
resonator for main clock oscillation.
System reset input
65
RESET
System is reset when low level is input to this pin.
Input
While this pin is low, oscillation of main clock is stopped.
Only
PD17P207-001 has internal pull-up resistor.
Output of the voltage regulator for the subclock oscillation
66
VREG
circuit.
Connect external 0.1-
F capacitor to this pin.
Output for detection of a program overrun.
N-channel,
High-
67
WDOUT
Outputs low level when the watchdog timer overflows or the
open drain
impedance
stack overflows/underflows. Use this pin after connecting to
the RESET pin.
68
XTIN
These pins are connected to a 32.768-kHz crystal oscillator
(Oscillates.)
69
XTOUT
for subclock oscillation.
71
VLCDC
Input to regulate the reference voltage to drive LCD.
70
VLCD0
Reference voltage outputs to drive LCD.
72
VLCD1
VLCD0:
Reference voltage output
73
VLCD2
VLCD1:
Doubler output (Two times the reference voltage)
VLCD2:
Tripler output (Three times the reference voltage)
74
CAPH
These pins are connected to a capacitor to boost the
––
75
CAPL
LCD drive voltage.
(Oscillation
stops.)
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