
μ
PD17717, 17718, 17719
116
Figure 12-1. Outline of Interrupt Block
Serial
interface 3
IPSIO3 flag
Serial
interface 2
IPSIO2 flag
Timer 3
IPTM3 flag
Timer 2
IPTM2 flag
Timer 1
IPTM1 flag
Timer 0
IPTM0 flag
INT4 pin
IP4 flag
INT3 pin
IP3 flag
INT2 pin
IP2 flag
INT1 pin
IP1 flag
INT0 pin
IP0 flag
CE pin
falling
IPCE flag
Program
counter
Address stack
registers
Stack
pointer
Interrupt stack
Pointer
Interrupt control block
Interrupt enable
flip-flop
DI, EI
instruction
IRQSIO3 flag
IRQSIO2 flag
IRQTM3 flag
IRQTM2 flag
IRQTM1 flag
IRQTM0 flag
IRQINT4 flag
IRQINT3 flag
IRQINT2 flag
IRQINT1 flag
IRQINT0 flag
IRQCE flag
Vector address
generator 01H
Vector address
generator 02H
Vector address
generator 03H
Vector address
generator 04H
Vector address
generator 05H
Vector address
generator 06H
Vector address
generator 07H
Vector address
generator 08H
Vector address
generator 09H
Vector address
generator 0AH
Vector address
generator 0BH
Vector address
generator 0CH
System
registers