
69
μ
PD17717, 17718, 17719
Table 8-1. Peripheral Hardware Control Functions of Control Registers (2/8)
Peripheral
Control Register
Peripheral Hardware Control Function
At Reset
Clock
Hardware
Name
Address
Read/
Function
Set value
Power-
WDT
CE
Stop
Write
Symbol
ON
& SP
reset
0
1
reset
reset
CE
CE reset timer
06H
R/W
CECNT3
Sets number of CE reset timer
1
Retained Retained
1
carry counter
CECNT2
carry counts
CECNT1
CECNT0
MOVT bit
07H
R/W
0
Fixed to “0”
0
0
0
Retained
selection
0
MOVTSEL1
Sets bit transferred by MOVT (transferred
MOVTSEL0
to DBF1, 0 during 8-bit transfer)
Serial
Serial I/O2
0AH
R/W
SIO2CLC
Controls P0A2/SCL pin level
Not affected
High impedance
0
0
0
0
interface interrupt timing
(I
2
C bus mode)
specification
SIO2WREL
Releases wait
Wait released status
Releases wait
register 1
SIO2WAT1
Controls wait and interrupt
0, 1: Issues at rising of 8th clock
request issuance (10 and 11
2: Issues at rising of 8th clock and waits
SIO2WAT0
are set in I
2
C bus mode)
3: Issues at rising of 9th clock and waits
Serial I/O2
0BH
R
0
Fixed to “0”
0
0
0
0
interrupt timing
SIO2CLD
Detects P0A2/SCL pin level
Low level
High level
specification
R/W
SIO2SIC
Selects interrupt source
Only on completion
On completion of
register 0
of transmission
transmission or on
detection of bus
release signal
SIO2SVAM
Selects bit of SIO2SVA used
Bits 0-7
Bits 1-7
Serial I/O2 SBI
0CH
R
SIO2CMDD Detects command signal
Does not detect
Detects
0
0
0
0
register 1
SIO2RELD
Detects bus release signal
Does not detect
Detects
R/W
SIO2CMDT
Controls trigger output of command
Automatically
Clears SO2 latch
signal
cleared after
after clearing flag
SIO2RELT
Controls trigger output of bus release
setting flag
Sets SO2 latch
signal
after setting flag
Serial I/O2 SBI
0DH
R/W
SIO2BSYE
Controls sync busy signal output
Disables output
Enables output
0
0
0
0
register 0
R
SIO2ACKD
Detects acknowledge signal
Does not detect
Detects
R/W
SIO2ACKE
Controls acknowledge signal output
Disables automatic Enables automatic
output
output
SIO2ACKT
Controls trigger output of
Does not output
Output immediately
acknowledge signal
acknowledge
after set
0: Setting prohibited
2: 2 counts
5: 5 counts
8: 8 counts
B: 11 counts C: 12 countsD: 13 counts
E: 14 counts F: 15 coounts
1: 1 count
3: 3 counts 4: 4 counts
6: 6 counts 7: 7 counts
9: 9 counts A: 10 counts
00
16-bit
transfer
01
0
High-order
8-bit transfer
1
1
Low-order
8-bit transfer
0
b
3
b
2
b
1
b
0