
304
μ
PD17717, 17718, 17719
<1> Setting of pin (to output serial data from TxD pin and input serial data from RxD pin)
1. Set the P0BBIO1 flag to “1” (output).
2. Set the port register of the TxD pin to “1” (at this point, the TxD pin outputs a high level).
3. Set the P0BBIO0 flag to “0” (input).
<2> Setting of interrupt
Execute the “EI” instruction and set the IPSIO3 flag to “1”.
<3> Setting of UART
1. Set the following in the serial I/O3 asynchronous mode register 1.
Parity bit
Character length
Stop bit
The number of stop bits is 1 during reception, regardless of the setting.
2. Set the following in the serial I/O3 asynchronous mode register 0.
UART mode (transmittion/reception)
Reception completion interrupt in case of reception error
Caution
Be sure to clear the SIO3CSIE flag to “0”.
<4> Set transmit data to the SIO3TXS register (start transmission)
UART transmission is started as soon as data has been set. The TxD pin outputs the start bit, transmit data
(7 or 8 bits), parity bit, and stop bit (1 or 2 bits) in that order, and the transmission is completed.
If the character length is 7 bits, however, the bit 7 (MSB) of the SIO3TXS register is ignored.
Detection of start bit
UART reception is started as soon as the start bit has been detected from the RxD pin. The RxD pin inputs
the start bit, transmit data (7 or 8 bits), parity bit, and stop bit (1 bit) in that order. The received data is
stored to the SIO3RXB register and the reception is completed.
<5> Interrupt routine (for transmission)
When the UART transmission operation is completed, the interrupt request flag IRQSIO3 is issued. When
this interrupt is accepted, execution branches to the vector address.
<6> Interrupt routine (for reception)
When the UART transmission operation is completed, the interrupt request flag IRQSIO3 is issued, and data
is set to the serial I/O3 asynchronous status register (however, only if a reception error occurs). When this
interrupt is accepted, execution branches to the vector address.
Caution
Because the serial I/O3 asynchronous status register is cleared to “0” when the
SIO3RXB register has been read, read the serial I/O3 asynchronous status register and
then the SIO3RXB register.