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參數(shù)資料
| 型號： | UPD17228MC |
| 廠商： | NEC Corp. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機(jī)的小型通用紅外遙控器 |
| 文件頁數(shù)： | 50/84頁 |
| 文件大?。?/td> | 393K |
| 代理商： | UPD17228MC |
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μ
PD17225, 17226, 17227, 17228
50
Data Sheet U12643EJ2V0DS00
9.
RESET
9.1
Reset by Reset Signal Input
When a low-level signal more than 50
μ
s is input to the RESET pin,
μ
PD17225 is reset.
When the system is reset, the oscillator circuit remains in the HALT mode and then enters an operation mode, like when
the STOP mode has been released. The wait time, after the reset signal has been removed, is 16.384 ms (f
X
= 4 MHz).
On power application, input the reset signal at least once because the internal circuitry operations are not stable. When
μ
PD17225 is reset, the following initialization takes place:
(1)
(2)
Program counter is reset to 0.
Flags in the register file are initialized to their default values (for the default values, refer to
Figure 11-1
Register Files
).
The default value (0320H) is written to the data buffer (DBF).
The hardware peripherals are initialized.
The system clock (f
X
) stops oscillation.
(3)
(4)
(5)
When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address
0 about 16 ms (at 4 MHz) later.
Figure 9-1. Reset Operation by RESET Input
RESET
Wait
Starts from address 0H
(about 16 ms at 4 MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Oscillation stops
9.2
Reset by Watchdog Timer (Connect RESET and WDOUT pins)
When the watchdog timer operates during program execution, a low level is output to the WDOUT pin, and the program
counter is reset to 0.
If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H.
Program so that the watchdog timer is reset at intervals of within 340 ms (at f
X
= 4 MHz) (set the WDTRES flag).
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