
μ
PD17225, 17226, 17227, 17228
17
Data Sheet U12643EJ2V0DS00
2.4.2
System registers (SYSREG)
The system registers are registers that are directly related to control of the CPU. These registers are mapped to
addresses 74H-7FH on the data memory and can be referenced regardless of bank specification.
The system registers include the following registers:
Address registers (AR0-AR3)
Note
Window register (WR)
Bank register (BANK)
Note
Memory pointer enable flag (MPE)
Memory pointers (MPH, MPL)
Index registers (IXH, IXM, IXL)
General register pointers (RPH, RPL)
Program status word (PSWORD)
Note
The address register (AR3) and the bank register (BANK) are fixed to 0 in the
μ
PD17225 and 17226.
Figure 2-5. Configuration of System Register
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
AR 3
AR 2
AR 1
AR 0
WR
BANK
IXH
IXM
IXL
RPH
RPL
PSW
MPH
MPL
Address register
(AR)
Window
register
(WR)
Bank
register
(BANK)
Data memory
row address
pointer (MP)
Index register
(IX)
General
register
pointer
(RP)
Program
status
word
(PSWORD)
0 0 0
0 0
0 0
0 0
M
P
E
B
C
D
C
M
P
C
Y Z
I
X
E
(RP)
(IX)
(MP)
(BANK)
Data
Bit
Symbol
Name
Address
Initial
Value
At
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Undefined
0
0
0
(WR)
*
*
*
*
(AR) ( PD17227, 17228)
(AR) ( PD17226)
(AR) ( PD17225)
μ
0 0 0 0 0
0 0 0 0
Note
*: This bit is fixed to 0 in the
μ
PD17225 and 17226.