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參數(shù)資料
| 型號(hào)： | UPD17228MC |
| 廠商： | NEC Corp. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機(jī)的小型通用紅外遙控器 |
| 文件頁(yè)數(shù)： | 41/84頁(yè) |
| 文件大?。?/td> | 393K |
| 代理商： | UPD17228MC |
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μ
PD17225, 17226, 17227, 17228
41
Data Sheet U12643EJ2V0DS00
7.2
Hardware of Interrupt Control Circuit
This section describes the flags of the interrupt control circuit.
(1)
Interrupt request flag and interrupt enable flag
The interrupt request flag (IRQ
×××
) is set to 1 when an interrupt request is generated, and is automatically
cleared to 0 when the interrupt processing is excuted.
An interrupt enable flag (IP
×××
) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt
is enabled; when it is 0, the interrupt is disabled.
(2)
EI/DI instruction
Whether an accepted interrupt is executed or not is specified by the EI or DI instruction.
When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The
INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by
an instruction.
The DI flag clears the INTE flag to 0 to disable all the interrupts.
The INTE flag is also cleared to 0 at reset, disabling all the interrupts.
Table 7-2. Interrupt Request Flags and Interrupt Enable Flag
Interrupt
Request Flag
Signal Setting Interrupt Request Flag
Interrupt
Enable Flag
IRQTM
Reset by 8-bit timer.
IPTM
IRQ
Set when edge of INT pin input signal is detected
IP
IRQBTM
Reset by basic interval timer.
IPBTM
7.2.1
INT
This flag reads the INT pin status.
When a high level is input to the INT pin, this flag is set to “1”; when a low level is input, the flag is reset to “0”.
3
2
1
0
0
0
0
INT
Address
RF : 0FH
INT
On reset
Undefined
R/W
R
0
1
INT Pin Level Detection
INT pin : Low level
INT pin : High level
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